Texas Instruments TMS380C26 specifications 68xxx DIO write timing, Suds Slds Sdtack

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

68xxx DIO write timing

NO.

PARAMETER

MIN

MAX

UNIT

255

Delay from

low to either

SUDS or

high

15

ns

SDTACK

SCS,

SLDS

262

Setup of write data valid before

or

no longer low

25

ns

SUDS

SLDS

263

Hold of write data valid after

or

high

25

ns

SUDS

SLDS

267§

Setup of register address before

or

no longer high (see Note 21)

15

ns

SUDS

SLDS

268

Hold of register address valid after

or

no longer low (see Note 22)

0

ns

SUDS

SLDS

272

Setup of SRNW before

or

no longer high (see Note 21)

15

ns

SUDS

SLDS

272a

Setup of inactive

or

high to active data strobe no longer high

55

ns

SUDS

SLDS

273

Hold of SRNW after

or

high

0

ns

SUDS

SLDS

273a

Hold of inactive

or

high after active data strobe high

55

ns

SUDS

SLDS

275

Delay from

or

high to

high (see Note 21)

35

ns

SCS,

SUDS

SLDS

SDTACK

Delay from

low in the first DIO access to the SIF register to

low in the

276³

SDTACK

SDTACK

4000

ns

immediately following access to the SIF

279²

Delay from

or

high to

high impedance

65

ns

SUDS

SLDS

SDTACK

280

Delay from

or

low to SDDIR low (see Note 21)

25

ns

SUDS

SLDS

281

Delay from

or

high to SDDIR high (see Note 21)

55

ns

SUDS

SLDS

281a

Hold of SDDIR low after

or

no longer active (see Note 21)

0

ns

SUDS

SLDS

If SIF register is

ready (no waiting

0

35

282b

Delay from SDBEN low to SDTACK low (see TMS380 Second Generation Token-

required)

ns

Ring User's Guide, SPWU005, subsection 3.4.1.1.1)

If SIF register is

not ready (waiting

0

4000

required)

282W

Delay from SDDIR low to

SDBEN

low

25

ns

283W

Delay from

or

high to

no longer low

25

ns

SUDS

SLDS

SDBEN

286

Pulse duration,

or

high between DIO accesses (see Note 21)

55

ns

SUDS

SLDS

²This specification is provided as an aid to board design.

³This specification has been characterized to meet stated value.

§ It is the later of SRD and SWR or SCS low that indicates the start of the cycle.

NOTES: 21. The ªinactiveº chip select is SIACKin DIO read and DIO write cycles, and SCS is the ªinactiveº chip select in interrupt acknowledge cycles.

22.In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0±SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0±SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters 266a and 264 are irrelevant, and parameter 268 must be met.

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