Texas Instruments TMS380C26 specifications = L, System Interface ± Motorola Mode SI/M, SBHE/ Srnw

					TMS380C26
				NETWORK COMMPROCESSOR
					SPWS010A±APRIL 1992±REVISED MARCH 1993
				Terminal Functions (continued)
					= L)
			System Interface ± Motorola Mode (SI/M
PIN NAME	NO.	I/O		DESCRIPTION
SADH0	73
SADH1	72		System Address/Data BusÐhigh byte (see Note 1).These lines make up the most significant byte
SADH2	71		of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit
SADH3	70	I/O	is SADH0, and the least significant bit is SADH7.
SADH4	69
			Address Multiplexing ² : Bits 31 ± 24 and bits 15 ± 8.
SADH5	68
SADH6	64		Data Multiplexing ² : Bits 15 ± 8.
SADH7	63
SADL0	54
SADL1	53		System Address/Data BusÐlow byte (see Note 1). These lines make up the least significant byte of
SADL2	52		each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is
SADL3	49	I/O	SADL0, and the least significant bit is SADL7.
SADL4	48
			Address Multiplexing ² : Bits 23 ± 16 and bits 7 ± 0.
SADL5	47
SADL6	46		Data Multiplexing ² : Bits 7 ± 0.
SADL7	45
			System Address Latch Enable. This is the enable pulse used to externally latch the 16 LSBs of the
SALE	43	OUT	address from the SADH0 ± SADH7 and SADL0 ± SADL7 buses at the start of the DMA cycle.
			Systems that implement address parity can also externally latch the parity bits (SPH and SPL) for
			the latched address.
			System Bus Busy. The TMS380C26 samples the value on this pin during arbitration. The sample has
			one of (2) two values (see Note 1):
SBBSY	31	IN
			H	= Not busy. The TMS380C26 may become Bus Master if the grant condition is met.
			L	= Busy. The TMS380C26 cannot become Bus Master.
SBCLK	44	IN	System Bus Clock. The TMS380C26 requires the external clock to synchronize its bus timings for
			all DMA transfers.

System Read Not Write. This pin serves as a control signal to indicate a read or write cycle.

SBHE/SRNW	57	I/O	H	=	Read Cycle (see Note 1).
			L	=	Write Cycle

System Bus Release. This pin indicates to the TMS380C26 that a higher-priority device requires the system bus. The value on this pin is ignored when the TMS380C26 is NOT perfoming DMA. This signal is internally synchronized to SBCLK.

SBRLS	30	IN
			H	=	The TMS380C26 can hold onto the system bus (see Note 1).
			L	=	The TMS380C26 should release the system bus upon completion of current DMA cycle. If the
					DMA transfer is not yet complete, the SIF will rearbitrate for the system bus.
			System Chip Select. Activates the system interface of TMS380C26 for a DIO read or write.
	29	IN
SCS			H	=	Not selected (see Note 1).
			L	=	Selected.
			System Data Bus Enable. This output signals to the external data buffers to begin driving data. This
			output is activated during both DIO and DMA.
SDBEN	58	OUT
			H	=	Keep external data buffers in high-impedance state.

L= Cause external data buffers to begin driving data.

²Typical bit ordering for Intel and Motorola processor buses.

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

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