Attached System Bus LAN Subsystem
Network Commprocessor
PIN Quad Flat Pack TOP View
Pinout
Description
Block diagram and signal descriptions
TMS380C26
Terminal Functions
PIN Name Description
AX3 AX2
Maxph
AX1 AX0
Maxpl
Mras
Sreset
Mreset OUT
MOE
NSELOUT0 NSELOUT1
Prtyen
Sbhe
= H
Sddir Direction DIO DMA
Shrq
Sintr
SWR
SRD
Syncin
108 Reserved. This signal must be left unconnected see Note
= Selects 8-bit mode see Note
= Selects 16-bit mode
System Interface ± Motorola Mode SI/M
= L
SBHE/ Srnw
Sirq
Terminal Functions = L
Sbgr
Sbrq
Suds
Sdtack
Slds
RCVR/RXD
FRAQ/TXD
Nsrt
Pxtalin
Lpbk
TXC
Coll
Terminal Functions
VSS4 VSS5 VSS6
Vssl
VSS1 VSS2
VSS3
Architecture
Communications processor CP
System interface SIF
Protocol handler PH
Memory interface MIF
Clock generator CG
Adapter support function ASF
Address Description
Adapter-Internal Pointers for Token-Ring²
Adapter-Internal Pointers for Ethernet ²
Byte Transfers
User-Access Hardware Registers
³ 68xxx Mode is always 16-bit
Word Transfers
Sifacl Register
Bits 0-2 Test 0±2. Value on Test 0±2 pins
Bit 5 Swddir Ð Current Sddir Signal Value
SIF Adapter Control Register Sifacl
Bit 10 Boot Ð Bootstrap CP Code
Bit 6 Swhrq Ð Current Shrq Signal Value
Bit 7 Psdmaen Ð Pseudo-System-DMA Enable
Bit 8 Areset Ð Adapter Reset
System Psdmaen Swhrq Swhlda Sinten Interrupt Result
Bit 12 Sinten Ð System-Interrupt Enable
Bit 13 PEN Ð Adapter Parity Enable
Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputs
Dmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten
Sifacl Control for Pseudo-DMA Operation
Systeminterrupt SINTR/SIRQ
DMA SHRQ/SBRQ
See Note
Recommended operating conditions
MIN NOM MAX Unit
Parameter Test Conditions MIN TYP MAX Unit
Output Under Test
Test measurement
High Low
Vload IOL
Reference Periods
When
Clkdiv = Oscout MBCLK1² MBCLK2²
Timing parameters
Static signals
Timing parameter symbology
Signal Function
HVDDH-RSL 118² Pulse duration High
289² ThRST Hold time of DMA size from High Intel mode only
Parameter MIN MAX Unit
Reaches minimum high level
101 106 104 105 102 107 110 108 109 111 117 118 119 288 289
VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT
Minimun VDD High Level
103
121 Hold time Valid after MBCLK1 low
126 Delay time from MBCLK1 no longer low to Valid
Mreset
NMI
Mreset
MBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl
MADH0±MADH7
Memory bus timing clocks, MRAS, MCAS, and MAL to Address
MADL0±MADL7 Maxph Maxpl
Mromen MAL
Column Status
Column Row
Address
Address Status
Maxph Maxpl
Memory bus timing read cycle
Mcas MOE
Maxph Maxpl MADH0±MADH7
Mbiaen
MAX0 MAX2 Mromen
Mras Mcas
Address Status Data/Parity
Memory bus timing write cycle
Mras Mcas Mben
Enable Address
MAX0, Address
MAX2 Mromen
Parameter MIN
Memory bus timing TMS380C26 releases control of bus
MBCLK1 MBCLK2 Mben
75a 74a
Mddir MAL Mbiaen Mbrq Mbgr
Setup time High before MBCLK1 rising edge, bus resume
Memory bus timing TMS380C26 resumes control of bus
Hold time Valid after MBCLK1 low, bus resume
Memory Bus Timing TMS380C26 Resumes Control of Bus
Mben Mddir MAL Mbiaen Mbrq Mbgr
Memory bus timing external bus master read from TMS380C26
Macs
Hold time Low after MBCLK2 low, external bus master read
MBCLK1 MBCLK2
MAX0 MAX2 Maxph Maxpl MADH0±MADH7
Mddir Macs
Memory bus timing external bus master write to TMS380C26
MAX0, MAX2 Maxph Maxpl
Data/Pty
Mcas Mref
Memory bus timing Dram refresh timing
MADL0±MADL7 Mras
73a
Xmatch Xfail
Xmatch and Xfail timing
Bit
127 128
Rcvr
Token ring Ð ring interface timing
Parameter MIN TYP MAX Unit
Rclk
160 159
Token ring Ð transmitter timing see Figure
Rclk or Pxtalin
Drvr
Txen
Ethernet timing of clock signals
Ethernet timing of Xmit signals
TXD
RXD
Ethernet timing of RCV signals Ð start of frame
CRS
RXC
322
Ethernet timing of RCV signals Ð end of frame
Crshld
320 321
Ethernet timing of RCV signals Ð no RXC
Norxc
TXD Txen
JAM
350
TXC TXD
Data
80x8x DIO read timing
Sdben
SCS, Srsx
SRS0± SRS2 Sbhe
Sras
80x8x DIO write timing
282W 283W 276 279 275 282b
Valid 264 265 268 256
267 272a 280 281
281a
287 First 286 Second
80x8x interrupt acknowledge timing ± first Siack pulse
80x8x interrupt acknowledge timing ± second Siack pulse
SRD, SWR SCS Siack
SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL
SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRD
Sddir High
Sdben SRDY²HI-Z
SWR Sown
80x8x mode bus arbitration timing, SIF takes control
Sown
SRD SWR
Sbbsy Shlda
SRD, SWR
SADL0±SADL7 SPH, SPL
High TwSCKL ±
After Sbclk low to guarantee recognition on this cycle
212 Delay from Sbclk low to address valid 214 ²
This cycle 208b
Sbclk Sras
Slds
80x8x mode DMA write timing
Sddir High
SRD High
SADL0±SADH7
SADH0±SADL7 SPH, SPL
80x8x mode bus arbitration timing, SIF returns control
208c
80x8x mode bus release timing
Sbrls Sown
TW or
68xxx DIO read timing
SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL
SRS0, SRS1
Siack Srnw
Suds Slds
Suds Slds Sdtack
68xxx DIO write timing
SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL
SCS SRSX, SRS0, SRS1 Siack Srnw
SDBEN³
SDTACK²
Siack Sdtack
68xxx interrupt acknowledge cycle timing
SCS Siack
SCS Srnw Sdtack
275 282a 255
SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw Slds
Sdben SDTACK² HI-Z
SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL
Sbrq
68xxx mode bus arbitration timing, SIF takes control
241 Delay from Sbclk high in TX cycle to High
Sbgr
SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL
Sberr Sdtack Sbbsy
SAS, Slds
Suds Srnw
Suds SAS
68xxx mode DMA read timing
237R Delay from Sbclk high in the T2 cycle to Low
On this cycle 208b
Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL
Sdben Suds Slds
68xxx mode DMA write timing
SADL0±SADH7, SADH0±SADL7 SPL, SPH
SAS
240 ² Setup SRNW,
68xxx mode bus arbitration timing, SIF returns control
Write Read
Sbclk Sbgr Sdtack
Read HI-Z Write
SIF HI-Z
Sberr Sdtack
68xxx mode bus release and error timing
Sown Sberr
Sbrls Sown
TH B TH E Sbclk Sdtack Sberr Shalt Sown
Rerun cycle with delayed start²
Normal completion with delayed start²
Sbclk Sdtack Sberr Shalt
MO±069±AD
Jedec plastic leaded quad flat package PQ suffix
254 0.010 NOM 635 0.025 NOM 76 0.030 NOM
Jedec NO. Outline Terminals MIN MAX
Important Notice