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PARAMETER MEASUREMENT INFORMATION

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

SIF Inputs:

SBCLK

SBGR

SDTACK

SIF Outputs:

SBRQ (see Note A)

SAS, SUDS,

SLDS

SRNW

SADH0±SADH7,

SADL0±SADL7,

SPH, SPL

SDDIR

SOWN

 

 

 

SIF Master

 

 

 

Bus Exchange

 

 

 

User

T2

T3

T4

 

I1

 

 

I2

T1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

230

220

240

240

223b

READ

HI-Z

WRITE

220

SIF

HI-Z

224d

WRITE

READ

224b

NOTE A: In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.

Figure 43. 68xxx Mode Bus Arbitration Timing, SIF Returns Control

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Texas Instruments TMS380C26 specifications Sbclk Sbgr Sdtack, Read HI-Z Write, Sif Hi-Z, Write Read