Texas Instruments TMS380C26 specs

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

80x8x mode bus arbitration timing, SIF returns control

NO.

PARAMETER

MIN MAX

UNIT

Delay from SBCLK low in I1 cycle to SADH0±SADH7, SADL0±SADL7, SPL, SPH,

and

220²

SRD,

SWR

35

ns

high-impedance

223b²

Delay from SBCLK low in I1 cycle to

high-impedance

45

ns

SBHE

224b

Delay from SBCLK low in cycle I2 to

high

25

ns

SOWN

224d

Delay from SBCLK low in cycle I2 to SDDIR high

30

ns

230

Delay from SBCLK high in cycle I1 to SHRQ low

25

ns

240²

Setup of

and

high-impedance before

no longer low

0

ns

SRD,

SWR,

SBHE

SOWN

²This specification has been characterized to meet stated value.

	SIF Master		Bus Exchange		User Master
T3	T4	I1	I2	(T1)	(T2)
SBCLK
SHLDA
SIF Outputs:		230
		230
SHRQ
(see Note A)		220
		220
SRD, SWR				HI-Z
			240
		223b
SBHE	SIF			HI-Z
SADH0±SADH7,	220		240
SADH0±SADH7,
SADL0±SADL7,	SIF			HI-Z
SPH, SPL			224d
			224d

WRITE

SDDIR

READ

224b

SOWN (see Note B)

NOTES: A. In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.

B. While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.

Figure 35. 80x8x Mode Bus Arbitration Timing, SIF Returns Control

POST OFFICE BOX 1443 •HOUSTON, TEXAS	73
77251±1443

Image 73

Texas Instruments TMS380C26 specifications 80x8x mode bus arbitration timing, SIF returns control

Contents

Attached System Bus LAN Subsystem Network Commprocessor PIN Quad Flat Pack TOP View Pinout Description Block diagram and signal descriptions Terminal Functions TMS380C26PIN Name Description AX1 AX0 MaxphMaxpl AX3 AX2 Mreset OUT SresetMOE Mras NSELOUT0 NSELOUT1 Prtyen Sbhe = H Shrq Sddir Direction DIO DMASintr SWR SRD = Selects 8-bit mode see Note 108 Reserved. This signal must be left unconnected see Note= Selects 16-bit mode Syncin = L System Interface ± Motorola Mode SI/MSBHE/ Srnw Sbgr Terminal Functions = LSbrq Sirq Sdtack SudsSlds Nsrt FRAQ/TXDPxtalin RCVR/RXD TXC LpbkColl Terminal Functions VSS1 VSS2 VsslVSS3 VSS4 VSS5 VSS6 Communications processor CP ArchitectureSystem interface SIF Protocol handler PH Memory interface MIF Clock generator CG Adapter support function ASF Address Description Adapter-Internal Pointers for Token-Ring² Adapter-Internal Pointers for Ethernet ² ³ 68xxx Mode is always 16-bit User-Access Hardware RegistersWord Transfers Byte Transfers Bit 5 Swddir Ð Current Sddir Signal Value Bits 0-2 Test 0±2. Value on Test 0±2 pinsSIF Adapter Control Register Sifacl Sifacl Register Bit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 6 Swhrq Ð Current Shrq Signal ValueBit 8 Areset Ð Adapter Reset Bit 10 Boot Ð Bootstrap CP Code Bit 13 PEN Ð Adapter Parity Enable Bit 12 Sinten Ð System-Interrupt EnableBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs System Psdmaen Swhrq Swhlda Sinten Interrupt Result Systeminterrupt SINTR/SIRQ Sifacl Control for Pseudo-DMA OperationDMA SHRQ/SBRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit See Note High Low Test measurementVload IOL Output Under Test When Reference PeriodsClkdiv = Oscout MBCLK1² MBCLK2² Timing parameter symbology Static signalsSignal Function Timing parameters Parameter MIN MAX Unit 289² ThRST Hold time of DMA size from High Intel mode onlyReaches minimum high level HVDDH-RSL 118² Pulse duration High Minimun VDD High Level VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT103 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 Mreset 126 Delay time from MBCLK1 no longer low to ValidNMI 121 Hold time Valid after MBCLK1 low MBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl MresetMADH0±MADH7 MADL0±MADL7 Maxph Maxpl Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMromen MAL Address Column RowAddress Status Column Status Mcas MOE Memory bus timing read cycleMaxph Maxpl MADH0±MADH7 Maxph Maxpl Mras Mcas MAX0 MAX2 MromenAddress Status Data/Parity Mbiaen Memory bus timing write cycle MAX0, Address Enable AddressMAX2 Mromen Mras Mcas Mben Parameter MIN Memory bus timing TMS380C26 releases control of bus 75a 74a MBCLK1 MBCLK2 MbenMddir MAL Mbiaen Mbrq Mbgr Memory bus timing TMS380C26 resumes control of bus Setup time High before MBCLK1 rising edge, bus resumeHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Macs Memory bus timing external bus master read from TMS380C26Hold time Low after MBCLK2 low, external bus master read MAX0 MAX2 Maxph Maxpl MADH0±MADH7 MBCLK1 MBCLK2Mddir Macs MAX0, MAX2 Maxph Maxpl Memory bus timing external bus master write to TMS380C26Data/Pty MADL0±MADL7 Mras Memory bus timing Dram refresh timing73a Mcas Mref Bit Xmatch and Xfail timing127 128 Xmatch Xfail Parameter MIN TYP MAX Unit Token ring Ð ring interface timingRclk Rcvr Rclk or Pxtalin Token ring Ð transmitter timing see FigureDrvr 160 159 Ethernet timing of Xmit signals Ethernet timing of clock signalsTXD Txen CRS Ethernet timing of RCV signals Ð start of frameRXC RXD Crshld Ethernet timing of RCV signals Ð end of frame320 321 322 Norxc Ethernet timing of RCV signals Ð no RXCTXD Txen TXC TXD 350Data JAM 80x8x DIO read timing SRS0± SRS2 Sbhe SCS, SrsxSras Sdben 80x8x DIO write timing 267 272a 280 281 Valid 264 265 268 256281a 282W 283W 276 279 275 282b 80x8x interrupt acknowledge timing ± second Siack pulse 80x8x interrupt acknowledge timing ± first Siack pulseSRD, SWR SCS Siack 287 First 286 Second Sddir High SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSdben SRDY²HI-Z SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL Sown 80x8x mode bus arbitration timing, SIF takes controlSRD SWR SWR Sown SRD, SWR Sbbsy ShldaSADL0±SADL7 SPH, SPL 212 Delay from Sbclk low to address valid 214 ² After Sbclk low to guarantee recognition on this cycleThis cycle 208b High TwSCKL ± Sbclk Sras Slds 80x8x mode DMA write timing SADL0±SADH7 SRD HighSADH0±SADL7 SPH, SPL Sddir High 80x8x mode bus arbitration timing, SIF returns control Sbrls Sown 80x8x mode bus release timingTW or 208c 68xxx DIO read timing Siack Srnw SRS0, SRS1Suds Slds SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL Suds Slds Sdtack 68xxx DIO write timing SDBEN³ SCS SRSX, SRS0, SRS1 Siack SrnwSDTACK² SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS Siack 68xxx interrupt acknowledge cycle timingSCS Srnw Sdtack Siack Sdtack Sdben SDTACK² HI-Z SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL 275 282a 255 241 Delay from Sbclk high in TX cycle to High 68xxx mode bus arbitration timing, SIF takes controlSbgr Sbrq SAS, Slds Sberr Sdtack SbbsySuds Srnw SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL 237R Delay from Sbclk high in the T2 cycle to Low 68xxx mode DMA read timingOn this cycle 208b Suds SAS Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timing SADL0±SADH7, SADH0±SADL7 SPL, SPH SAS 240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns control Read HI-Z Write Sbclk Sbgr SdtackSIF HI-Z Write Read Sown Sberr 68xxx mode bus release and error timingSbrls Sown Sberr Sdtack Normal completion with delayed start² Rerun cycle with delayed start²Sbclk Sdtack Sberr Shalt TH B TH E Sbclk Sdtack Sberr Shalt Sown 254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec plastic leaded quad flat package PQ suffixJedec NO. Outline Terminals MIN MAX MO±069±AD Important Notice