TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

68xxx interrupt acknowledge cycle timing

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

MIN MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

255

Delay from

 

 

 

 

 

 

 

 

 

 

 

low to either

 

 

 

 

 

 

 

 

 

or

 

 

 

 

or

 

high

15

 

ns

SDTACK

 

SCS

SUDS,

SIACK

 

259²

Hold of SAD high-impedance after

 

 

 

 

 

 

 

 

 

no longer high (see Note 21)

0

 

ns

SIACK

 

 

260

Setup of output data valid before

 

 

 

 

 

 

 

 

 

 

 

 

 

 

no longer high

0

 

ns

SDTACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

261²

Delay from

 

 

 

 

 

 

high to SAD high-impedance (see Note 21)

35

ns

SIACK

 

261a

Hold of output data valid after

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

no longer low (see Note 21)

0

 

ns

SCS

 

SIACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

267§

Setup of register address before

 

 

 

 

 

 

 

 

 

 

 

 

no longer high (see Note 21)

15

 

ns

SIACK

 

272a

Setup of inactive high

 

 

 

 

 

to active data strobe no longer high

55

 

ns

SIACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

273a

Hold of inactive SRNW high after active data strobe high

55

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

275

Delay from

 

 

 

 

 

or

 

 

 

 

 

 

 

high to

 

 

 

 

 

 

 

 

 

 

 

 

high (see Note 21)

35

ns

SCS

SRNW

 

SDTACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Delay from

 

 

 

 

 

 

 

 

 

 

low in the first DIO access to the SIF register to

 

low in the immediately

 

 

 

276³

SDTACK

SDTACK

4000

ns

following access to the SIF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

279²

Delay from

 

 

 

 

 

 

 

 

high to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

high impedance

65

ns

SIACK

SDTACK

 

282a

Delay from

 

 

 

 

 

 

 

 

 

low to

 

 

 

 

 

 

 

 

 

 

 

 

 

low in a read cycle

35

ns

SDBEN

SDTACK

 

 

 

 

 

 

 

 

 

 

 

Delay from

 

 

 

 

 

low to

 

 

 

 

 

 

 

 

 

 

low (see TMS380 Second Generation Token-Ring User's Guide,

 

 

 

282R

SIACK

SDBEN

55

ns

SPWU005, subsection 3.4.1.1.1) provided the previous cycle completed

 

 

 

 

 

 

 

 

 

 

 

 

283R

Delay from

 

 

 

 

 

 

high to

 

 

 

 

 

 

 

 

 

high (see Note 21)

35

ns

SIACK

SDBEN

 

 

 

 

 

286

Pulse duration,

 

 

 

 

 

 

 

 

 

high between DIO accesses (see Note 21)

55

 

ns

SIACK

 

²This specification is provided as an aid to board design.

³This specification has been characterized to meet stated value.

§It is the later of SRD and SRD or SCS low that indicates the start of the cycle.

NOTE 21: The ªinactiveº chip select is SIACKin DIO read and DIO write cycles, and SCS is the ªinactiveº chip select in interrupt acknowledge cycles.

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79

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Texas Instruments TMS380C26 68xxx interrupt acknowledge cycle timing, SCS Siack, SCS Srnw Sdtack, Siack Sdtack