Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL | Texas Instruments TMS380C26

84

PARAMETER MEASUREMENT INFORMATION

					TWAIT
T4	TX	T1		T2	V	T3	T4	T1
T4	TX	T1		T2		T3	T4	T1
	S1	S2	S3	S4	S5	S6	S7
SBCLK
	222

SAS (see Note A)

210

SUDS,

SLDS

218

(High)

239

209 223R

239

209

217

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SRNW	216	217
SRNW		215
		215
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1443 •HOUSTON, TEXAS 77001

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SADL0±SADH7,

SADH0±SADL7,

SPH, SPL

SDTACK (see Notes B and C)

SDDIR

SDBEN (see Note A)

216	218	216a
	215

229

	212
212	233a			206
233	233	214	205	207a
233	233	214		207a
	Address		Data In	HI-Z
Extended Address		247²		207b
			208a
		208b
	237R			225R

²If parameter 208a is not met, then valid data must be present before SDTACK goes low. NOTES: A. Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.

B.All VSS pins should be routed to minimize inductance to system ground.

C.On read cycle, read strobe remains active until the internal sample of incoming data is completed. Input-data may be removed when either the read strobe or SDBEN becomes no longer active.

Figure 41. 68xxx Mode DMA Read Timing

Image 84

Texas Instruments TMS380C26 specifications Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL

Contents

Network Commprocessor Attached System Bus LAN Subsystem Pinout PIN Quad Flat Pack TOP View Description Block diagram and signal descriptions TMS380C26 Terminal FunctionsPIN Name Description Maxph AX1 AX0Maxpl AX3 AX2 Sreset Mreset OUTMOE Mras Prtyen NSELOUT0 NSELOUT1 = H Sbhe Sddir Direction DIO DMA ShrqSintr SRD SWR 108 Reserved. This signal must be left unconnected see Note = Selects 8-bit mode see Note= Selects 16-bit mode Syncin System Interface ± Motorola Mode SI/M = LSBHE/ Srnw Terminal Functions = L SbgrSbrq Sirq Suds SdtackSlds FRAQ/TXD NsrtPxtalin RCVR/RXD Lpbk TXCColl Terminal Functions Vssl VSS1 VSS2VSS3 VSS4 VSS5 VSS6 Architecture Communications processor CPSystem interface SIF Memory interface MIF Protocol handler PH Adapter support function ASF Clock generator CG Adapter-Internal Pointers for Token-Ring² Address Description Adapter-Internal Pointers for Ethernet ² User-Access Hardware Registers ³ 68xxx Mode is always 16-bitWord Transfers Byte Transfers Bits 0-2 Test 0±2. Value on Test 0±2 pins Bit 5 Swddir Ð Current Sddir Signal ValueSIF Adapter Control Register Sifacl Sifacl Register Bit 6 Swhrq Ð Current Shrq Signal Value Bit 7 Psdmaen Ð Pseudo-System-DMA EnableBit 8 Areset Ð Adapter Reset Bit 10 Boot Ð Bootstrap CP Code Bit 12 Sinten Ð System-Interrupt Enable Bit 13 PEN Ð Adapter Parity EnableBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs System Psdmaen Swhrq Swhlda Sinten Interrupt Result Sifacl Control for Pseudo-DMA Operation Systeminterrupt SINTR/SIRQDMA SHRQ/SBRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit See Note Test measurement High LowVload IOL Output Under Test Reference Periods WhenClkdiv = Oscout MBCLK1² MBCLK2² Static signals Timing parameter symbologySignal Function Timing parameters 289² ThRST Hold time of DMA size from High Intel mode only Parameter MIN MAX UnitReaches minimum high level HVDDH-RSL 118² Pulse duration High VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT Minimun VDD High Level103 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 126 Delay time from MBCLK1 no longer low to Valid MresetNMI 121 Hold time Valid after MBCLK1 low Mreset MBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph MaxplMADH0±MADH7 Memory bus timing clocks, MRAS, MCAS, and MAL to Address MADL0±MADL7 Maxph MaxplMromen MAL Column Row AddressAddress Status Column Status Memory bus timing read cycle Mcas MOEMaxph Maxpl MADH0±MADH7 Maxph Maxpl MAX0 MAX2 Mromen Mras McasAddress Status Data/Parity Mbiaen Memory bus timing write cycle Enable Address MAX0, AddressMAX2 Mromen Mras Mcas Mben Memory bus timing TMS380C26 releases control of bus Parameter MIN MBCLK1 MBCLK2 Mben 75a 74aMddir MAL Mbiaen Mbrq Mbgr Setup time High before MBCLK1 rising edge, bus resume Memory bus timing TMS380C26 resumes control of busHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Memory bus timing external bus master read from TMS380C26 MacsHold time Low after MBCLK2 low, external bus master read MBCLK1 MBCLK2 MAX0 MAX2 Maxph Maxpl MADH0±MADH7Mddir Macs Memory bus timing external bus master write to TMS380C26 MAX0, MAX2 Maxph MaxplData/Pty Memory bus timing Dram refresh timing MADL0±MADL7 Mras73a Mcas Mref Xmatch and Xfail timing Bit127 128 Xmatch Xfail Token ring Ð ring interface timing Parameter MIN TYP MAX UnitRclk Rcvr Token ring Ð transmitter timing see Figure Rclk or PxtalinDrvr 160 159 Ethernet timing of clock signals Ethernet timing of Xmit signalsTXD Txen Ethernet timing of RCV signals Ð start of frame CRSRXC RXD Ethernet timing of RCV signals Ð end of frame Crshld320 321 322 Ethernet timing of RCV signals Ð no RXC NorxcTXD Txen 350 TXC TXDData JAM 80x8x DIO read timing SCS, Srsx SRS0± SRS2 SbheSras Sdben 80x8x DIO write timing Valid 264 265 268 256 267 272a 280 281281a 282W 283W 276 279 275 282b 80x8x interrupt acknowledge timing ± first Siack pulse 80x8x interrupt acknowledge timing ± second Siack pulseSRD, SWR SCS Siack 287 First 286 Second SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRD Sddir HighSdben SRDY²HI-Z SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL 80x8x mode bus arbitration timing, SIF takes control SownSRD SWR SWR Sown Sbbsy Shlda SRD, SWRSADL0±SADL7 SPH, SPL After Sbclk low to guarantee recognition on this cycle 212 Delay from Sbclk low to address valid 214 ²This cycle 208b High TwSCKL ± Sbclk Sras 80x8x mode DMA write timing Slds SRD High SADL0±SADH7SADH0±SADL7 SPH, SPL Sddir High 80x8x mode bus arbitration timing, SIF returns control 80x8x mode bus release timing Sbrls SownTW or 208c 68xxx DIO read timing SRS0, SRS1 Siack SrnwSuds Slds SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL 68xxx DIO write timing Suds Slds Sdtack SCS SRSX, SRS0, SRS1 Siack Srnw SDBEN³SDTACK² SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL 68xxx interrupt acknowledge cycle timing SCS SiackSCS Srnw Sdtack Siack Sdtack SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw Slds Sdben SDTACK² HI-ZSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL 275 282a 255 68xxx mode bus arbitration timing, SIF takes control 241 Delay from Sbclk high in TX cycle to HighSbgr Sbrq Sberr Sdtack Sbbsy SAS, SldsSuds Srnw SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL 68xxx mode DMA read timing 237R Delay from Sbclk high in the T2 cycle to LowOn this cycle 208b Suds SAS Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL 68xxx mode DMA write timing Sdben Suds Slds SAS SADL0±SADH7, SADH0±SADL7 SPL, SPH 68xxx mode bus arbitration timing, SIF returns control 240 ² Setup SRNW, Sbclk Sbgr Sdtack Read HI-Z WriteSIF HI-Z Write Read 68xxx mode bus release and error timing Sown SberrSbrls Sown Sberr Sdtack Rerun cycle with delayed start² Normal completion with delayed start²Sbclk Sdtack Sberr Shalt TH B TH E Sbclk Sdtack Sberr Shalt Sown Jedec plastic leaded quad flat package PQ suffix 254 0.010 NOM 635 0.025 NOM 76 0.030 NOMJedec NO. Outline Terminals MIN MAX MO±069±AD Important Notice