2 Troubleshooting Procedures | 2.5 FDD TroubleshootingSystem Board Troubleshooting |
Table
LED Status | Test item | Message |
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(02H) | Initialization of CMOS data (1) |
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| Setting of IRT status | (Boot status and IRT busy flag, the remaining bit is 0.) |
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| Storing DRAM size in CMOS |
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03H | Resume branch (at Cold Boot) | Not resume when a CMOS error occurred |
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| Not resume when resume status code is not set |
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| Resume error check |
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| 1CH Power Failure error (Resume error 7AH) |
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| |
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| Check of memory configuration change (Resume error |
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| 73H) |
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| RAM area checksum check in system BIOS (Resume |
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| error 79H) |
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| PnP RAM checksum check (Resume error 77H) |
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| Transition to |
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| Resume error | Reset of CPU clock to low |
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| Prohibition of all SMI |
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| Clearance of resume status |
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| Return to ROM |
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| Designating the area of |
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| (Prohibition of DRAM) |
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| Setting of resume error request |
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| System BIOS ROM/RAM copy |
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04H | SM RAM initialization |
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| Check of Wake Up factor |
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| Rewriting of SMRAM base and |
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| Storing CPU state map for BIOS |
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| Enabling SMI only by ASMI |
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05H | Initialization of a device which | PIT test (at Cold Boot) and initialization |
| needs initialization before |
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| Setting of test pattern for PIT#0 CH0 | |
| initialization of PCI bus | |
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| |
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| Check whether the test pattern set can be read. |
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| Initialization of PIT CH0 (Setting of timer interrupt interval |
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| to 55ms) |
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| Initialization of PIT CH2 (Setting of sound generator |
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| frequency to 664Hz) |
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| Test of PIT CH1 (Check whether a refresh signal is |
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| working properly when refresh interval is set to 30ms. |
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| HLT when the time is out.) |
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|
TECRA M1 Maintenance Manual |
