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Xilinx V2.1 manual Xilinx System Generator v2.1 Reference Guide, Xilinx Development System

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Parameters speciﬁc to the Gateway Out block are:

Xilinx System Generator v2.1 Reference Guide

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-69: Gateway Out block parameters dialog box

Parameters speciﬁc to the Gateway Out block are:

∙IOB Timing Constraint: input/output buffers (IOBs). IOBs. They are None, Data Attribute.

In hardware, a Gateway Out is realized as a set of There are three ways to constrain the timing on Rate, and Data Rate, Set 'FAST'

If None is selected, no timing constraints for the IOBs are put in the user constraint ﬁle (.ucf) produced by System Generator. This means the paths from the IOBs to synchronous elements are not constrained.

If Data Rate is selected, the IOBs are constrained at the data rate at which the IOBs operate. The rate is determined by System Clock Period provided on the System Generator block and the sample rate of the Gateway relative to the other sample periods in the design. For example, the following OFFSET = OUT constraints are generated for a Gateway Out named 'Dout' that is running at the system period of 10 ns:

# Offset out constraints

NET "Dout<0>" OFFSET = OUT : 10.0 : AFTER "clk";

NET "Dout<1>" OFFSET = OUT : 10.0 : AFTER "clk";

NET "Dout<2>" OFFSET = OUT : 10.0 : AFTER "clk";

NET "Dout_valid" OFFSET = OUT : 10.0 : AFTER "clk"; NET "Dout_valid" FAST;

It should be noted there is a valid bit that accompanies the data signal. It is constrained at the same rate. For more information concerning the valid bit, refer to the Hardware Handshaking section in Chapter 1 of this manual.

If Data Rate, Set 'FAST' Attribute is selected, the OFFSET = OUT constraints described above are produced. In addition, a FAST slew rate attribute is generated for each IOB. This reduces delay but increases noise and power consumption. For the previous example, the following additional attributes are added to the .ucf ﬁle

NET "Dout<0>" FAST;

NET "Dout<1>" FAST;

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Xilinx V2.1 manual Xilinx System Generator v2.1 Reference Guide, Parameters speciﬁc to the Gateway Out block are

Contents

Printed in U.S.A Xilinx Blocks System Generator Software FeaturesUsing the Xilinx Software Auxiliary Files Xilinx System Generator v2.1 forManual Contents About This ManualXilinx System Generator v2.1 Reference Guide Xilinx Development SystemResource Additional ResourcesDescription/URL Conventions Typographical>> cd <your $MATLAB home directory> Xilinx System Generator v2.1 Reference GuideContents ChapterIntroduction Chapter 2 Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter 5 Using the Xilinx Software Chapter 4 System Generator Software FeaturesChapter 6 Auxiliary Files Chapter Introduction Industry and Product OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator System Level Modeling with System GeneratorIntroduction System GeneratorXilinx System Generator v2.1 Reference Guide The System Generator Design FlowXilinx Development System The System Generator Design Flow LibraryMATLAB Environment SimulinkXilinx System Generator v2.1 Reference Guide Arithmetic Data TypesXilinx Development System Hardware Handshaking Multirate SystemsHardware Handshaking IntroductionBit-Trueand Cycle-TrueModeling Automatic Testbench GenerationXilinx System Generator v2.1 Reference Guide Xilinx Development SystemWhat is a Xilinx Block? What is a Xilinx Block?Chapter Xilinx Blockset Overview Xilinx Blockset OverviewThe Nature of Signals in the Xilinx Blockset The Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemThe Nature of Signals in the Xilinx Blockset Valid and Invalid DataPort Data Types Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Licensed CoresXilinx Development System Common Options in Block Parameters Dialog Box Xilinx LogiCORE VersionsCommon Options in Block Parameters Dialog Box Xilinx Blockset OverviewUse Placement Information for Core Arithmetic TypeImplement with Xilinx Smart-IP Core if possible Generate CorePrecision Number of BitsOverﬂow and Quantization Override with DoublesSample Period Use Explicit Sample PeriodXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter Xilinx Blocks Basic ElementsSystem Generator Xilinx BlocksBlock Parameters Dialog Box ∙Xilinx Product Family∙Target Directory ∙System Clock Period∙Global Clock Enable and Global Clear ∙Override with Doubles∙Generate Cores ∙Generate buttonAddressable Shift Register Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlack Box Incorporating mixed language black boxesBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-3:Black Box block parameters dialog box Xilinx BlocksBasic Elements Concat Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideConstant ConvertBlock Parameters Dialog Box Xilinx BlocksCounter Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-7:Convert block parameters dialog boxXilinx Blocks Basic ElementsBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-8:Counter block parameters dialog box Xilinx Development SystemDelay Xilinx LogiCOREBlock Parameters Dialog Box Xilinx BlocksDown Sample Xilinx System Generator v2.1 Reference GuideFigure 3-11:Down sample circuit behavior Xilinx Development SystemGet Valid Bit Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Figure 3-13:Mux block parameters dialog boxParallel to Serial Block InterfaceXilinx Blocks Basic ElementsRegister Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Interface Block Parameters Dialog BoxXilinx Blocks Figure 3-16:Register block parameters dialog boxXilinx System Generator v2.1 Reference Guide ReinterpretXilinx Development System Serial to Parallel Block Parameters Dialog boxXilinx Blocks Basic ElementsBlock Interface Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areSet Valid Bit SliceBlock Parameters Dialog Box Xilinx BlocksBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-21:Slice block operation Xilinx Development SystemXilinx Blocks SyncBasic Elements Figure 3-23:Sync block use Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Parameters Dialog Box Xilinx BlocksFigure 3-26:Sync block parameters dialog box Basic ElementsXilinx System Generator v2.1 Reference Guide Up SampleXilinx Development System Block Parameters Dialog Box Xilinx BlocksFigure 3-29:Up Sample block parameters dialog box Basic ElementsCommunication Convolutional EncoderBlock Interface Xilinx System Generator v2.1 Reference GuideCommunication Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksDepuncture Xilinx System Generator v2.1 Reference GuideFigure 3-32:Example of Depuncture block use Xilinx Development SystemInterleaver Deinterleaver Block Parameters Dialog BoxXilinx Blocks CommunicationFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Interface Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide PunctureXilinx Development System RS Decoder Block Parameters Dialog BoxXilinx Blocks Figure 3-38:Puncture block parameters dialog boxBlock Interface Xilinx System Generator v2.1 Reference GuideThe port descriptions are Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxCommunication Xilinx System Generator v2.1 Reference Guide g x = ∏ x –ahxGS + i i =Xilinx Development System RS Encoder LatencyXilinx LogiCore Xilinx Blocksg x = x –ai x –ai + 1 . . . . x –ai + 2t c x = g x ⋅ ig x = x –a0 x –a1 x –a2 . . . . x –a15 Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block InterfaceCommunication Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the RS Encoder block are Xilinx Development SystemXilinx Blocks g x = ∏ x –ahxGS + i i =Communication Viterbi Decoder LatencyXilinx LogiCore Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Block InterfaceCommunication Xilinx System Generator v2.1 Reference Guide Xilinx LogiCoreXilinx Development System Xilinx Blocks Block InterfaceFigure 3-46:Pipelined decimator and interpolator Block Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Figure 3-47:CIC block parameters dialog boxXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-49:DDS block parameters dialog box Xilinx Development SystemXilinx LogiCORE X k = ∑ xmW N mkXilinx Blocks W N = e Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-51 FFT Timing Diagram Block TimingXilinx Blocks Figure 3-52:FFT Timing Characteristics Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Interface yn = ∑ hixn –iXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-53:FIR block parameters dialog box Xilinx Development SystemMath AccumulatorMath Xilinx LogiCOREBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areAddSub Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksCMult Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-56:CMult block parameters dialog boxInverter Xilinx LogiCOREXilinx Blocks MathLogical Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks Figure 3-58:Logical block parameters dialog boxMult Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Xilinx LogiCOREMath Negate RelationalBlock Parameters Dialog Box Xilinx LogiCOREBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks MathScale ShiftBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideSineCosine Block Parameters Dialog BoxXilinx Blocks Figure 3-64:Shift block parameters dialog boxBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the SineCosine block areThreshold Latency Using BlockXilinx Blocks Maximum CoreEnabled Subsystems MATLAB I/OGateway Blocks Block Parameters Dialog BoxEnable Adapter Gateway InMATLAB I/O Xilinx BlocksParameters speciﬁc to the Gateway In block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Gateway OutMATLAB I/O Parameters speciﬁc to the Gateway Out block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Quantization Error Blocks Clear Quantization ErrorQuantization Error DisplayMemory Dual Port RAMBlock Interface Xilinx System Generator v2.1 Reference GuideXilinx Blocks MemoryFigure 3-70:Illustration of write modes Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the block are Xilinx Development Systemlog 2d Xilinx LogiCOREXilinx Blocks DepthFIFO Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-72:FIFO block parameters dialog boxXilinx Blocks Xilinx LogiCOREMemory Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-73:ROM block parameters dialog box Xilinx Development SystemXilinx LogiCORE log 2dXilinx Blocks DepthSingle Port RAM Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxMemory Figure 3-75:Illustration of write modes Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx LogiCORE log 2dXilinx Blocks MemoryState Machine Mealy State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemState Machine Xilinx BlocksMoore State Machine Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks Figure 3-80:Moore State Machine block diagramState Machine Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-82:Construction of Next State and Output matrices Xilinx Development SystemRegistered Mealy State Machine Xilinx LogiCOREXilinx Blocks State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxState Machine depth = 2k 2i = 2k + width = k + o N = depth × width = k + o2k +Xilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks Registered Moore State MachineState Machine Xilinx System Generator v2.1 Reference Guide Xilinx Development Systemds = 2k 2i = 2k + N s = ds × ws = k 2k +Block Parameters Dialog Box Xilinx BlocksXilinx LogiCORE Xilinx System Generator v2.1 Reference Guidewhere Xilinx Development SystemChapter System Generator Software Features Using the System Generator installerSystem Generator Software Features >>setupUsing Black Boxes Installed System Generator directoryA Black Box Example Xilinx System Generator v2.1 Reference GuideUsing Black Boxes Black Box windowSystem Generator Software Features Figure 4-1:Output of example black box functionUse of mixed language projects Incorporating mixed language black boxesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Use of mixed language projectsFigure 4-2:Black Box block parameters dialog box Tips for creating a high performance design Data Rate, Set ‘FAST’ AttributeXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUsing the System Generator Constraints Files Using the System Generator Constraints FilesSystem Clock Period Multicycle Path ConstraintsIOB Timing and Placement Constraints Example for showing constraints useXilinx System Generator v2.1 Reference Guide Figure 4-4:Example of a multirate designSystem Generator Software Features Using the System Generator Constraints FilesImportant Issues Constraints FilesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features Xilinx System Generator v2.1 Reference Guide ∙sysgen.log - log ﬁleXilinx Development System Chapter Using the Xilinx Software Using the Xilinx SoftwareXilinx ISE 4.1i Project Navigator Opening a System Generator projectXilinx System Generator v2.1 Reference Guide Implementing your designXilinx Development System Using the Xilinx Software Xilinx ISE 4.1i Project NavigatorFigure 5-6:Properties of simulation process Xilinx System Generator v2.1 Reference GuideXilinx Development System Using an EDIF software ﬂow Using an EDIF software flowSimulation Compiling your IPXilinx System Generator v2.1 Reference Guide MXE librariesXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Chapter Auxiliary Files Demonstration designsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemPerl scripts Auxiliary Files>> demo perl <scriptname> -hXilinx System Generator v2.1 Reference Guide Xilinx Development System