Manuals / Xilinx / Household Appliance / Smoke Alarm

Xilinx V2.1 manual Using an EDIF software ﬂow, Simulation, Compiling your IP, ModelSim PE or EE/SE

Models: V2.1

1 148

Download 148 pages 48.7 Kb

Page 143

Using an EDIF software ﬂow

Using the Xilinx Software

were generated in Simulink. Provided that your design was error free, the ModelSim console window will report that the simulation ﬁnished without errors.

Your installed version of ModelSim (either MXE or ModelSim EE/SE/PE) must be associated with the Project Navigator tool for this interaction to work. To associate ModelSim with the Project Navigator, follow the instructions in the Simulation section, later in this chapter.

Using an EDIF software ﬂow

You may not wish to use the Project Navigator for your VHDL synthesis. If you choose to run a synthesis compiler in a standalone software tool, then you will generate EDIF. You may wish to import your EDIF ﬁles into the Project Navigator.

To do this, open the Project Navigator and select File >> New Project. A new project properties dialog will open. Select EDIF as the design ﬂow type.

Figure 5-8: EDIF design ﬂow in Project Navigator

Now you may add your EDIF ﬁles to the project as sources. From the Project Navigator pulldown menu bar, choose Project>>Add Source, and then browse to your EDIF ﬁles.

Simulation

The System Generator creates custom .do ﬁles for use with your generated project and a ModelSim simulator. To use these ﬁles, you must have ModelSim (PE or EE/SE) or the Xilinx Edition of ModelSim (MXE). You may run your simulations from the standalone ModelSim tool, or you may associate it with the Xilinx 4.1i ISE Project Navigator, and run your simulations from within Project Navigator as part of the full software implementation ﬂow.

Compiling your IP

You must compile your IP (cores) libraries with ModelSim before you can simulate.

ModelSim (PE or EE/SE)

To compile your IP with ModelSim (PE or EE/SE) you will need to download a TCL/ TK script from the Xilinx web site, and run it to compile these libraries:

Xilinx Simprim

Unisim

XilinxCoreLib

Using an EDIF software flow

143

Image 143

Xilinx V2.1 Using an EDIF software ﬂow, Simulation, Compiling your IP, ModelSim PE or EE/SE, Using an EDIF software flow

Contents

Xilinx System Generator v2.1 for Printed in U.S.AXilinx Blocks System Generator Software Features Using the Xilinx Software Auxiliary FilesXilinx Development System Manual ContentsAbout This Manual Xilinx System Generator v2.1 Reference GuideDescription/URL Additional ResourcesResource Xilinx System Generator v2.1 Reference Guide ConventionsTypographical >> cd <your $MATLAB home directory>Chapter 2 Xilinx Blockset Overview ContentsChapter IntroductionXilinx Development System Xilinx System Generator v2.1 Reference GuideChapter 6 Auxiliary Files Chapter 4 System Generator Software FeaturesChapter 5 Using the Xilinx Software Xilinx Development System Chapter IntroductionIndustry and Product Overview Xilinx System Generator v2.1 Reference GuideSystem Generator System GeneratorSystem Level Modeling with System Generator IntroductionXilinx Development System The System Generator Design FlowXilinx System Generator v2.1 Reference Guide Simulink The System Generator Design FlowLibrary MATLAB EnvironmentXilinx Development System Arithmetic Data TypesXilinx System Generator v2.1 Reference Guide Introduction Hardware HandshakingMultirate Systems Hardware HandshakingXilinx Development System Bit-Trueand Cycle-TrueModelingAutomatic Testbench Generation Xilinx System Generator v2.1 Reference GuideXilinx Blockset Overview What is a Xilinx Block?What is a Xilinx Block? Chapter Xilinx Blockset OverviewXilinx Development System The Nature of Signals in the Xilinx BlocksetThe Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blockset Overview The Nature of Signals in the Xilinx BlocksetValid and Invalid Data Port Data TypesXilinx Development System Licensed CoresXilinx System Generator v2.1 Reference Guide Xilinx Blockset Overview Common Options in Block Parameters Dialog BoxXilinx LogiCORE Versions Common Options in Block Parameters Dialog BoxGenerate Core Use Placement Information for CoreArithmetic Type Implement with Xilinx Smart-IP Core if possibleOverride with Doubles PrecisionNumber of Bits Overﬂow and QuantizationXilinx Development System Sample PeriodUse Explicit Sample Period Xilinx System Generator v2.1 Reference GuideXilinx Blocks Chapter Xilinx BlocksBasic Elements System Generator∙System Clock Period Block Parameters Dialog Box∙Xilinx Product Family ∙Target Directory∙Generate button ∙Global Clock Enable and Global Clear∙Override with Doubles ∙Generate CoresXilinx Development System Addressable Shift RegisterBlock Interface Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx LogiCOREBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Black BoxIncorporating mixed language black boxes Block Parameters Dialog BoxBasic Elements Xilinx BlocksFigure 3-3:Black Box block parameters dialog box Xilinx System Generator v2.1 Reference Guide ConcatBlock Interface Block Parameters Dialog BoxXilinx Blocks ConstantConvert Block Parameters Dialog BoxFigure 3-7:Convert block parameters dialog box CounterBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx BlocksXilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-8:Counter block parameters dialog boxXilinx Blocks DelayXilinx LogiCORE Block Parameters Dialog BoxXilinx Development System Down SampleXilinx System Generator v2.1 Reference Guide Figure 3-11:Down sample circuit behaviorBasic Elements Get Valid BitBlock Parameters Dialog Box Xilinx BlocksFigure 3-13:Mux block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideBasic Elements Parallel to SerialBlock Interface Xilinx BlocksXilinx Development System RegisterBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-16:Register block parameters dialog box Block InterfaceBlock Parameters Dialog Box Xilinx BlocksXilinx Development System ReinterpretXilinx System Generator v2.1 Reference Guide Basic Elements Serial to ParallelBlock Parameters Dialog box Xilinx BlocksParameters speciﬁc to the block are Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Set Valid BitSlice Block Parameters Dialog BoxXilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-21:Slice block operationBasic Elements SyncXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-23:Sync block use Basic Elements Block Parameters Dialog BoxXilinx Blocks Figure 3-26:Sync block parameters dialog boxXilinx Development System Up SampleXilinx System Generator v2.1 Reference Guide Basic Elements Block Parameters Dialog BoxXilinx Blocks Figure 3-29:Up Sample block parameters dialog boxXilinx System Generator v2.1 Reference Guide CommunicationConvolutional Encoder Block InterfaceXilinx Blocks CommunicationBlock Parameters Dialog Box Xilinx LogiCOREXilinx Development System DepunctureXilinx System Generator v2.1 Reference Guide Figure 3-32:Example of Depuncture block useCommunication Interleaver DeinterleaverBlock Parameters Dialog Box Xilinx BlocksXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Xilinx Blocks Block InterfaceBlock Parameters Dialog Box Xilinx LogiCOREXilinx Development System PunctureXilinx System Generator v2.1 Reference Guide Figure 3-38:Puncture block parameters dialog box RS DecoderBlock Parameters Dialog Box Xilinx BlocksXilinx Development System Block InterfaceXilinx System Generator v2.1 Reference Guide The port descriptions areCommunication Block Parameters Dialog BoxXilinx Blocks Xilinx Development System g x = ∏ x –ahxGS + i i =Xilinx System Generator v2.1 Reference Guide Xilinx Blocks RS EncoderLatency Xilinx LogiCoreXilinx System Generator v2.1 Reference Guide g x = x –ai x –ai + 1 . . . . x –ai + 2tc x = g x ⋅ i g x = x –a0 x –a1 x –a2 . . . . x –a15Communication Block InterfaceXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the RS Encoder block areCommunication g x = ∏ x –ahxGS + i i =Xilinx Blocks Xilinx System Generator v2.1 Reference Guide Viterbi DecoderLatency Xilinx LogiCoreCommunication Block InterfaceBlock Parameters Dialog Box Xilinx Development System Xilinx LogiCoreXilinx System Generator v2.1 Reference Guide Figure 3-46:Pipelined decimator and interpolator Block InterfaceXilinx Blocks Figure 3-47:CIC block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-49:DDS block parameters dialog boxXilinx Blocks X k = ∑ xmW N mkXilinx LogiCORE Xilinx System Generator v2.1 Reference Guide W N = eBlock Interface Block Parameters Dialog BoxXilinx Blocks Block TimingFigure 3-51 FFT Timing Diagram Xilinx Development System Figure 3-52:FFT Timing CharacteristicsXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks yn = ∑ hixn –iBlock Interface Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-53:FIR block parameters dialog boxXilinx LogiCORE MathAccumulator MathParameters speciﬁc to the block are Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks AddSubBlock Parameters Dialog Box Xilinx LogiCOREFigure 3-56:CMult block parameters dialog box CMultBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideMath InverterXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide LogicalBlock Parameters Dialog Box Xilinx LogiCOREFigure 3-58:Logical block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx Development System MultBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideMath Xilinx LogiCOREXilinx Blocks Xilinx LogiCORE NegateRelational Block Parameters Dialog BoxMath Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide ScaleShift Block Parameters Dialog BoxFigure 3-64:Shift block parameters dialog box SineCosineBlock Parameters Dialog Box Xilinx BlocksParameters speciﬁc to the SineCosine block are Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideMaximum Core ThresholdLatency Using Block Xilinx BlocksBlock Parameters Dialog Box Enabled SubsystemsMATLAB I/O Gateway BlocksXilinx Blocks Enable AdapterGateway In MATLAB I/OXilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway In block are MATLAB I/O Gateway OutXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway Out block are Display Quantization Error BlocksClear Quantization Error Quantization ErrorXilinx System Generator v2.1 Reference Guide MemoryDual Port RAM Block InterfaceFigure 3-70:Illustration of write modes MemoryXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areDepth log 2dXilinx LogiCORE Xilinx BlocksFigure 3-72:FIFO block parameters dialog box FIFOBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideMemory Xilinx LogiCOREXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-73:ROM block parameters dialog boxDepth Xilinx LogiCORElog 2d Xilinx BlocksXilinx Development System Single Port RAMBlock Interface Xilinx System Generator v2.1 Reference GuideMemory Block Parameters Dialog BoxXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-75:Illustration of write modes Memory Xilinx LogiCORElog 2d Xilinx BlocksXilinx Development System State MachineMealy State Machine Xilinx System Generator v2.1 Reference GuideXilinx Blocks State MachineXilinx System Generator v2.1 Reference Guide Moore State MachineBlock Parameters Dialog Box Xilinx LogiCOREState Machine Figure 3-80:Moore State Machine block diagramXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-82:Construction of Next State and Output matricesState Machine Registered Mealy State MachineXilinx LogiCORE Xilinx BlocksXilinx Development System Xilinx System Generator v2.1 Reference GuideState Machine Block Parameters Dialog BoxXilinx Blocks Xilinx System Generator v2.1 Reference Guide depth = 2k 2i = 2k +width = k + o N = depth × width = k + o2k + Xilinx LogiCOREState Machine Registered Moore State MachineXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideXilinx Blocks ds = 2k 2i = 2k +N s = ds × ws = k 2k + Block Parameters Dialog BoxXilinx Development System Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide where>>setup Chapter System Generator Software FeaturesUsing the System Generator installer System Generator Software FeaturesXilinx System Generator v2.1 Reference Guide Using Black BoxesInstalled System Generator directory A Black Box ExampleFigure 4-1:Output of example black box function Using Black BoxesBlack Box window System Generator Software FeaturesXilinx Development System Use of mixed language projectsIncorporating mixed language black boxes Xilinx System Generator v2.1 Reference GuideFigure 4-2:Black Box block parameters dialog box Use of mixed language projectsSystem Generator Software Features Xilinx Development System Tips for creating a high performance designData Rate, Set ‘FAST’ Attribute Xilinx System Generator v2.1 Reference GuideMulticycle Path Constraints Using the System Generator Constraints FilesUsing the System Generator Constraints Files System Clock PeriodFigure 4-4:Example of a multirate design IOB Timing and Placement ConstraintsExample for showing constraints use Xilinx System Generator v2.1 Reference GuideUsing the System Generator Constraints Files System Generator Software FeaturesXilinx Development System Important IssuesConstraints Files Xilinx System Generator v2.1 Reference GuideSystem Generator Software Features Files automatically created by System GeneratorFiles automatically created by System Generator Xilinx Development System ∙sysgen.log - log ﬁleXilinx System Generator v2.1 Reference Guide Opening a System Generator project Chapter Using the Xilinx SoftwareUsing the Xilinx Software Xilinx ISE 4.1i Project NavigatorXilinx Development System Implementing your designXilinx System Generator v2.1 Reference Guide Xilinx ISE 4.1i Project Navigator Using the Xilinx SoftwareXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 5-6:Properties of simulation process Compiling your IP Using an EDIF software ﬂowUsing an EDIF software flow SimulationXilinx Development System MXE librariesXilinx System Generator v2.1 Reference Guide Using the Xilinx Software Xilinx software tools resourcesXilinx software tools resources Xilinx Development System Chapter Auxiliary FilesDemonstration designs Xilinx System Generator v2.1 Reference Guideperl <scriptname> -h Perl scriptsAuxiliary Files >> demoXilinx Development System Xilinx System Generator v2.1 Reference Guide