Xilinx System Generator v2.1 Reference Guide
In the Simulink environment, the Override with Doubles option allows you to simulate the entire design in double precision floating point.
This option is useful in selecting fixed point widths or when debugging. If you detect unacceptable quahtization errors with fixed point signals, you can choose to simulate your entire design, or only specific blocks, using double precision floating point signals and arithmetic operations. This option will help you discover which part of your design is responsible for the unacceptable quantization error.
You may choose Override with Doubles on a particular block. You may also choose this option for an entire sheet or an entire subsystem (the sheet plus underlying hierarchy) by instantiating a System Generator token on the sheet, and choosing Override with Doubles as one of the System Generator block’s configurable parameters.
When the output of one block with Override with Doubles set is connected to the input of another block where the option is also set, data samples are transmitted in double precision.
You can easily identify which blocks are currently set to Override with Doubles. When this option is set, affected Xilinx blocks are displayed in gray rather than the normal blue or yellow.
Sample Period
Data streams are processed at a specific sample rate as they flow through Simulink. Typically, each block detects the input sample rate and produces the correct sample rate on its output. Xilinx blocks Up Sample and Down Sample provide a means to increase or decrease sample rates.
Use Explicit Sample Period
If you select Use Explicit Sample Period rather than the default, you may set the sample period required for all the block outputs. This is useful when implementing features such as feedback loops in your design. In a feedback loop, it is not possible for the System Generator to determine a default sample rate, because the loop makes an input sample rate depend on a
The following image (the Concat block’s parameters dialog box) shows the options with Use Explicit Sample Period selected.
Figure
22 | Xilinx Development System |