Xilinx Blocks
The Next State Matrix and the Output Array are composed in the following way:
Figure
The rows of the matrices correspond to the current state. The next state matrix has one columns for each input value. The output array has only one column since the input value does not affect the output of the state machine.
Block Parameters Dialog Box
The block parameters dialog can be invoked by
Figure
The next state logic, state register, is implemented using the Xilinx Block RAM LogiCORE. A separate Block RAM LogiCORE is used to implement the output logic and output register.
The number of bits used to implement the state logic and state register is given by the equations:
ds = (2k )(2i ) = 2k + i
ws = k
N s = ds × ws = (k )(2k + i )
State Machine | 125 |