Xilinx V2.1 manual Contents, Chapter, Introduction, Xilinx Blockset Overview

Contents
Chapter 1	Introduction
	Industry and Product Overview	8
	System Generator	9
	System Level Modeling with System Generator	9
	The System Generator Design Flow	10
	Arithmetic Data Types	12
	Hardware Handshaking	13
	Multirate Systems	13
	Bit-True and Cycle-True Modeling	14
	Automatic Testbench Generation	14
Chapter 2 Xilinx Blockset Overview
	What is a Xilinx Block?	15
	Instantiating Xilinx Blocks within a Simulink Model	16
	The Block Parameters Dialog Box	16
	The Nature of Signals in the Xilinx Blockset	16
	Use of Xilinx Smart-IP Cores by the System Generator	18
	Licensed Cores	18
	Xilinx LogiCORE Versions	19
	Common Options in Block Parameters Dialog Box	19
	Arithmetic Type	20
	Implement with Xilinx Smart-IP Core (if possible)	20
	Generate Core	20
	Latency	20
	Precision	21
	Number of Bits	21
	Overflow and Quantization	21
	Override with Doubles	21
	Sample Period	22
Chapter 3	Xilinx Blocks
	Basic Elements	23
	System Generator	23
	Addressable Shift Register	26
	Black Box	28

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