System Generator Software Features
enter information describing clocks, parameter names, types and values as appropriate.
Figure 4-2: Black Box block parameters dialog box
Creating mixed language synthesis and simulation projects
The following describes how to synthesize mixed language designs using Synplify and Leonardo Spectrum synthesis compilers, and how to test using the ModelSim simulator. The XST synthesis compiler does not support mixed language designs.
To synthesize using Synplify, open the project file (for example,
my_project_synplicity.prj) in Synplify. Tell the tool to add your black box files to the project. The procedure for a Leonardo Spectrum project is analogous, except that the project filename example is my_project_leon.tcl.
To run a behavioral simulation in ModelSim, edit the vcom.do and vsim.do files that were produced by System Generator. The vcom.do file must be augmented with lines to compile the black box VHDL and Verilog. For each black box VHDL file, add a line of the form
vcom <file>
where <file> is the name of the file. Similarly, each Verilog file needs a line of the form
vlog <file>
In addition, you must add a
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