Xilinx V2.1 manual Using the System Generator Constraints Files, System Clock Period

System Generator Software Features

enable or clear port may result in large fanout signals, thus degrading system performance.

Figure 4-3: Use Global Port selections if necessary

∙Use cross-probing between the Xilinx Timing Analyzer and Leonardo or Synplify Pro to identify critical paths. Design hierarchy is preserved when using the Leonardo or Synplify project files that System Generator creates, thus making it easy to correlate between the Timing Analyzer report and the Simulink model. For more information refer to Xilinx Application note 406 at http://www.xilinx.com/xapp/xapp406.pdf

Using the System Generator Constraints Files

When System Generator transforms a design into HDL, it also writes a constraints file (also known as a ucf file). Constraints tell downstream tools how to process the design. With the assistance of constraints, downstream tools can produce a higher quality implementation than otherwise could have been obtained, and can do so using considerably less time. Constraints supply the following information:

∙The period to be used for the system clock.

∙The speed, with respect to the system clock, at which various portions of the design must run.

∙The pin locations at which ports should be placed.

∙The speed at which ports must operate.

System Clock Period

The system clock period (i.e., the period of the fastest clock in the design) can be specified in the System Generator block. System Generator writes this period to the constraints file, and the downstream tools use the period as a goal when implementing the design.

The example below shows the constraints that specify the system clock period.

Multicycle Path Constraints

Many designs consist of parts that run at different clock rates. For the fastest parts, the system clock period is used, and for the remaining parts, the clock period is an integer multiple of the system clock period. It is important that downstream tools know what speed each part of the design must achieve. With this information, efficiency and effectiveness of the tools are greatly increased, resulting in reduced compilation times and improved hardware realizations.

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