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V2.1 manual Xilinx System Generator v2.1 Reference Guide, Xilinx Development System
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52:FFT Timing Characteristics
Install
51 FFT Timing Diagram
Use Placement Information for Core
Important Issues
Quantization Error Blocks
Delay
The Nature of Signals in the Xilinx Blockset
What is
∙Global Clock Enable and Global Clear
Page 148
Image 148
Xilinx System Generator v2.1 Reference Guide
148
Xilinx Development System
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Image 148
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Contents
Printed in U.S.A
Xilinx Blocks System Generator Software Features
Using the Xilinx Software Auxiliary Files
Xilinx System Generator v2.1 for
Manual Contents
About This Manual
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Resource
Additional Resources
Description/URL
Conventions
Typographical
>> cd <your $MATLAB home directory>
Xilinx System Generator v2.1 Reference Guide
Contents
Chapter
Introduction
Chapter 2 Xilinx Blockset Overview
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Chapter 5 Using the Xilinx Software
Chapter 4 System Generator Software Features
Chapter 6 Auxiliary Files
Chapter Introduction
Industry and Product Overview
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
System Generator
System Level Modeling with System Generator
Introduction
System Generator
Xilinx System Generator v2.1 Reference Guide
The System Generator Design Flow
Xilinx Development System
The System Generator Design Flow
Library
MATLAB Environment
Simulink
Xilinx System Generator v2.1 Reference Guide
Arithmetic Data Types
Xilinx Development System
Hardware Handshaking
Multirate Systems
Hardware Handshaking
Introduction
Bit-Trueand Cycle-TrueModeling
Automatic Testbench Generation
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
What is a Xilinx Block?
What is a Xilinx Block?
Chapter Xilinx Blockset Overview
Xilinx Blockset Overview
The Nature of Signals in the Xilinx Blockset
The Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
The Nature of Signals in the Xilinx Blockset
Valid and Invalid Data
Port Data Types
Xilinx Blockset Overview
Xilinx System Generator v2.1 Reference Guide
Licensed Cores
Xilinx Development System
Common Options in Block Parameters Dialog Box
Xilinx LogiCORE Versions
Common Options in Block Parameters Dialog Box
Xilinx Blockset Overview
Use Placement Information for Core
Arithmetic Type
Implement with Xilinx Smart-IP Core if possible
Generate Core
Precision
Number of Bits
Overflow and Quantization
Override with Doubles
Sample Period
Use Explicit Sample Period
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Chapter Xilinx Blocks
Basic Elements
System Generator
Xilinx Blocks
Block Parameters Dialog Box
∙Xilinx Product Family
∙Target Directory
∙System Clock Period
∙Global Clock Enable and Global Clear
∙Override with Doubles
∙Generate Cores
∙Generate button
Addressable Shift Register
Block Interface
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Xilinx LogiCORE
Block Parameters Dialog Box
Xilinx Blocks
Basic Elements
Black Box
Incorporating mixed language black boxes
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-3:Black Box block parameters dialog box
Xilinx Blocks
Basic Elements
Concat
Block Interface
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Constant
Convert
Block Parameters Dialog Box
Xilinx Blocks
Counter
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-7:Convert block parameters dialog box
Xilinx Blocks
Basic Elements
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-8:Counter block parameters dialog box
Xilinx Development System
Delay
Xilinx LogiCORE
Block Parameters Dialog Box
Xilinx Blocks
Down Sample
Xilinx System Generator v2.1 Reference Guide
Figure 3-11:Down sample circuit behavior
Xilinx Development System
Get Valid Bit
Block Parameters Dialog Box
Xilinx Blocks
Basic Elements
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Figure 3-13:Mux block parameters dialog box
Parallel to Serial
Block Interface
Xilinx Blocks
Basic Elements
Register
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Block Interface
Block Parameters Dialog Box
Xilinx Blocks
Figure 3-16:Register block parameters dialog box
Xilinx System Generator v2.1 Reference Guide
Reinterpret
Xilinx Development System
Serial to Parallel
Block Parameters Dialog box
Xilinx Blocks
Basic Elements
Block Interface
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Parameters specific to the block are
Set Valid Bit
Slice
Block Parameters Dialog Box
Xilinx Blocks
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-21:Slice block operation
Xilinx Development System
Xilinx Blocks
Sync
Basic Elements
Figure 3-23:Sync block use
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Block Parameters Dialog Box
Xilinx Blocks
Figure 3-26:Sync block parameters dialog box
Basic Elements
Xilinx System Generator v2.1 Reference Guide
Up Sample
Xilinx Development System
Block Parameters Dialog Box
Xilinx Blocks
Figure 3-29:Up Sample block parameters dialog box
Basic Elements
Communication
Convolutional Encoder
Block Interface
Xilinx System Generator v2.1 Reference Guide
Communication
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx Blocks
Depuncture
Xilinx System Generator v2.1 Reference Guide
Figure 3-32:Example of Depuncture block use
Xilinx Development System
Interleaver Deinterleaver
Block Parameters Dialog Box
Xilinx Blocks
Communication
Figure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Block Interface
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx Blocks
Xilinx System Generator v2.1 Reference Guide
Puncture
Xilinx Development System
RS Decoder
Block Parameters Dialog Box
Xilinx Blocks
Figure 3-38:Puncture block parameters dialog box
Block Interface
Xilinx System Generator v2.1 Reference Guide
The port descriptions are
Xilinx Development System
Xilinx Blocks
Block Parameters Dialog Box
Communication
Xilinx System Generator v2.1 Reference Guide
g x = ∏ x –ahxGS + i i =
Xilinx Development System
RS Encoder
Latency
Xilinx LogiCore
Xilinx Blocks
g x = x –ai x –ai + 1 . . . . x –ai + 2t
c x = g x ⋅ i
g x = x –a0 x –a1 x –a2 . . . . x –a15
Xilinx System Generator v2.1 Reference Guide
Xilinx Blocks
Block Interface
Communication
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Parameters specific to the RS Encoder block are
Xilinx Development System
Xilinx Blocks
g x = ∏ x –ahxGS + i i =
Communication
Viterbi Decoder
Latency
Xilinx LogiCore
Xilinx System Generator v2.1 Reference Guide
Block Parameters Dialog Box
Block Interface
Communication
Xilinx System Generator v2.1 Reference Guide
Xilinx LogiCore
Xilinx Development System
Xilinx Blocks
Block Interface
Figure 3-46:Pipelined decimator and interpolator
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Figure 3-47:CIC block parameters dialog box
Xilinx Blocks
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-49:DDS block parameters dialog box
Xilinx Development System
Xilinx LogiCORE
X k = ∑ xmW N mk
Xilinx Blocks
W N = e
Block Interface
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-51 FFT Timing Diagram
Block Timing
Xilinx Blocks
Figure 3-52:FFT Timing Characteristics
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Block Interface
yn = ∑ hixn –i
Xilinx Blocks
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-53:FIR block parameters dialog box
Xilinx Development System
Math
Accumulator
Math
Xilinx LogiCORE
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Parameters specific to the block are
AddSub
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx Blocks
CMult
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-56:CMult block parameters dialog box
Inverter
Xilinx LogiCORE
Xilinx Blocks
Math
Logical
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx Blocks
Figure 3-58:Logical block parameters dialog box
Mult
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Xilinx Blocks
Xilinx LogiCORE
Math
Negate
Relational
Block Parameters Dialog Box
Xilinx LogiCORE
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx Blocks
Math
Scale
Shift
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
SineCosine
Block Parameters Dialog Box
Xilinx Blocks
Figure 3-64:Shift block parameters dialog box
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Parameters specific to the SineCosine block are
Threshold
Latency Using Block
Xilinx Blocks
Maximum Core
Enabled Subsystems
MATLAB I/O
Gateway Blocks
Block Parameters Dialog Box
Enable Adapter
Gateway In
MATLAB I/O
Xilinx Blocks
Parameters specific to the Gateway In block are
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Xilinx Blocks
Gateway Out
MATLAB I/O
Parameters specific to the Gateway Out block are
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Quantization Error Blocks
Clear Quantization Error
Quantization Error
Display
Memory
Dual Port RAM
Block Interface
Xilinx System Generator v2.1 Reference Guide
Xilinx Blocks
Memory
Figure 3-70:Illustration of write modes
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Parameters specific to the block are
Xilinx Development System
log 2d
Xilinx LogiCORE
Xilinx Blocks
Depth
FIFO
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-72:FIFO block parameters dialog box
Xilinx Blocks
Xilinx LogiCORE
Memory
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-73:ROM block parameters dialog box
Xilinx Development System
Xilinx LogiCORE
log 2d
Xilinx Blocks
Depth
Single Port RAM
Block Interface
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Xilinx Blocks
Block Parameters Dialog Box
Memory
Figure 3-75:Illustration of write modes
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Xilinx LogiCORE
log 2d
Xilinx Blocks
Memory
State Machine
Mealy State Machine
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
State Machine
Xilinx Blocks
Moore State Machine
Block Parameters Dialog Box
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Xilinx Blocks
Figure 3-80:Moore State Machine block diagram
State Machine
Block Parameters Dialog Box
Xilinx System Generator v2.1 Reference Guide
Figure 3-82:Construction of Next State and Output matrices
Xilinx Development System
Registered Mealy State Machine
Xilinx LogiCORE
Xilinx Blocks
State Machine
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Xilinx Blocks
Block Parameters Dialog Box
State Machine
depth = 2k 2i = 2k +
width = k + o N = depth × width = k + o2k +
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
Xilinx Blocks
Registered Moore State Machine
State Machine
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
ds = 2k 2i = 2k +
N s = ds × ws = k 2k +
Block Parameters Dialog Box
Xilinx Blocks
Xilinx LogiCORE
Xilinx System Generator v2.1 Reference Guide
where
Xilinx Development System
Chapter System Generator Software Features
Using the System Generator installer
System Generator Software Features
>>setup
Using Black Boxes
Installed System Generator directory
A Black Box Example
Xilinx System Generator v2.1 Reference Guide
Using Black Boxes
Black Box window
System Generator Software Features
Figure 4-1:Output of example black box function
Use of mixed language projects
Incorporating mixed language black boxes
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
System Generator Software Features
Use of mixed language projects
Figure 4-2:Black Box block parameters dialog box
Tips for creating a high performance design
Data Rate, Set ‘FAST’ Attribute
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Using the System Generator Constraints Files
Using the System Generator Constraints Files
System Clock Period
Multicycle Path Constraints
IOB Timing and Placement Constraints
Example for showing constraints use
Xilinx System Generator v2.1 Reference Guide
Figure 4-4:Example of a multirate design
System Generator Software Features
Using the System Generator Constraints Files
Important Issues
Constraints Files
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Files automatically created by System Generator
Files automatically created by System Generator
System Generator Software Features
Xilinx System Generator v2.1 Reference Guide
∙sysgen.log - log file
Xilinx Development System
Chapter Using the Xilinx Software
Using the Xilinx Software
Xilinx ISE 4.1i Project Navigator
Opening a System Generator project
Xilinx System Generator v2.1 Reference Guide
Implementing your design
Xilinx Development System
Using the Xilinx Software
Xilinx ISE 4.1i Project Navigator
Figure 5-6:Properties of simulation process
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Using an EDIF software flow
Using an EDIF software flow
Simulation
Compiling your IP
Xilinx System Generator v2.1 Reference Guide
MXE libraries
Xilinx Development System
Xilinx software tools resources
Xilinx software tools resources
Using the Xilinx Software
Chapter Auxiliary Files
Demonstration designs
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
Perl scripts
Auxiliary Files
>> demo
perl <scriptname> -h
Xilinx System Generator v2.1 Reference Guide
Xilinx Development System
