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Xilinx V2.1 manual Block Interface, Block Parameters Dialog Box, Communication

Models: V2.1

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			Xilinx Blocks

	Constraint	Optimal convolution codes for	Optimal convolution codes for
	length	decoding 1/2 rate encoders	decoding 1/3 rate encoders
9		111101101, 110011011	111101101, 110011011, 100100111

Block Interface

The Viterbi Decoder has either two or three input ports and one output port. The decoder can have either two or three input ports depending on the conﬁgurable parameter indicating encoder output rate. Use of hard coding requires input data to be 1 bit wide. Soft coding requires the input data to be 3 to 8 bits (inclusive). The output

port is of type UFix1_0.

Note - This version of the Viterbi Decoder is not recommended for implementation of punctured codes.

Block Parameters Dialog Box

Figure 3-45: Viterbi Decoder block parameters dialog box

Parameters speciﬁc to the Viterbi Decoder block are:

∙Encoder Output Rate: 2 or 3. must match the output rate on the Convolutional Encoder from which data is being decoded.

Communication

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Xilinx V2.1 manual Block Interface, Block Parameters Dialog Box, Communication

Contents

Xilinx Blocks System Generator Software Features Printed in U.S.AUsing the Xilinx Software Auxiliary Files Xilinx System Generator v2.1 forAbout This Manual Manual ContentsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemAdditional Resources ResourceDescription/URL Typographical Conventions>> cd <your $MATLAB home directory> Xilinx System Generator v2.1 Reference GuideChapter ContentsIntroduction Chapter 2 Xilinx Blockset OverviewXilinx Development System Xilinx System Generator v2.1 Reference GuideChapter 4 System Generator Software Features Chapter 5 Using the Xilinx SoftwareChapter 6 Auxiliary Files Industry and Product Overview Chapter IntroductionXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Level Modeling with System Generator System GeneratorIntroduction System GeneratorThe System Generator Design Flow Xilinx System Generator v2.1 Reference GuideXilinx Development System Library The System Generator Design FlowMATLAB Environment SimulinkArithmetic Data Types Xilinx System Generator v2.1 Reference GuideXilinx Development System Multirate Systems Hardware HandshakingHardware Handshaking IntroductionAutomatic Testbench Generation Bit-Trueand Cycle-TrueModelingXilinx System Generator v2.1 Reference Guide Xilinx Development SystemWhat is a Xilinx Block? What is a Xilinx Block?Chapter Xilinx Blockset Overview Xilinx Blockset OverviewThe Block Parameters Dialog Box The Nature of Signals in the Xilinx BlocksetXilinx System Generator v2.1 Reference Guide Xilinx Development SystemValid and Invalid Data The Nature of Signals in the Xilinx BlocksetPort Data Types Xilinx Blockset OverviewLicensed Cores Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx LogiCORE Versions Common Options in Block Parameters Dialog BoxCommon Options in Block Parameters Dialog Box Xilinx Blockset OverviewArithmetic Type Use Placement Information for CoreImplement with Xilinx Smart-IP Core if possible Generate CoreNumber of Bits PrecisionOverﬂow and Quantization Override with DoublesUse Explicit Sample Period Sample PeriodXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBasic Elements Chapter Xilinx BlocksSystem Generator Xilinx Blocks∙Xilinx Product Family Block Parameters Dialog Box∙Target Directory ∙System Clock Period∙Override with Doubles ∙Global Clock Enable and Global Clear∙Generate Cores ∙Generate buttonBlock Interface Addressable Shift RegisterXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks Basic ElementsIncorporating mixed language black boxes Black BoxBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Figure 3-3:Black Box block parameters dialog boxBasic Elements Block Interface ConcatBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideConvert ConstantBlock Parameters Dialog Box Xilinx BlocksBlock Parameters Dialog Box CounterXilinx System Generator v2.1 Reference Guide Figure 3-7:Convert block parameters dialog boxBasic Elements Xilinx BlocksXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-8:Counter block parameters dialog box Xilinx Development SystemXilinx LogiCORE DelayBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Down SampleFigure 3-11:Down sample circuit behavior Xilinx Development SystemBlock Parameters Dialog Box Get Valid BitXilinx Blocks Basic ElementsXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-13:Mux block parameters dialog boxBlock Interface Parallel to SerialXilinx Blocks Basic ElementsBlock Parameters Dialog Box RegisterXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Block InterfaceXilinx Blocks Figure 3-16:Register block parameters dialog boxReinterpret Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Parameters Dialog box Serial to ParallelXilinx Blocks Basic ElementsBlock Parameters Dialog Box Block InterfaceXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areSlice Set Valid BitBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-21:Slice block operation Xilinx Development SystemSync Xilinx BlocksBasic Elements Xilinx System Generator v2.1 Reference Guide Figure 3-23:Sync block useXilinx Development System Xilinx Blocks Block Parameters Dialog BoxFigure 3-26:Sync block parameters dialog box Basic ElementsUp Sample Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Block Parameters Dialog BoxFigure 3-29:Up Sample block parameters dialog box Basic ElementsConvolutional Encoder CommunicationBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box CommunicationXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide DepunctureFigure 3-32:Example of Depuncture block use Xilinx Development SystemBlock Parameters Dialog Box Interleaver DeinterleaverXilinx Blocks CommunicationXilinx System Generator v2.1 Reference Guide Figure 3-34:Forney convolutional interleaver with a constant difference between consecutive branchesXilinx Development System Block Parameters Dialog Box Block InterfaceXilinx LogiCORE Xilinx BlocksPuncture Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Parameters Dialog Box RS DecoderXilinx Blocks Figure 3-38:Puncture block parameters dialog boxXilinx System Generator v2.1 Reference Guide Block InterfaceThe port descriptions are Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksCommunication g x = ∏ x –ahxGS + i i = Xilinx System Generator v2.1 Reference GuideXilinx Development System Latency RS EncoderXilinx LogiCore Xilinx Blocksc x = g x ⋅ i g x = x –ai x –ai + 1 . . . . x –ai + 2tg x = x –a0 x –a1 x –a2 . . . . x –a15 Xilinx System Generator v2.1 Reference GuideBlock Interface Xilinx BlocksCommunication Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxParameters speciﬁc to the RS Encoder block are Xilinx Development Systemg x = ∏ x –ahxGS + i i = Xilinx BlocksCommunication Latency Viterbi DecoderXilinx LogiCore Xilinx System Generator v2.1 Reference GuideBlock Interface Block Parameters Dialog BoxCommunication Xilinx LogiCore Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Interface Xilinx BlocksFigure 3-46:Pipelined decimator and interpolator Xilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-47:CIC block parameters dialog boxXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-49:DDS block parameters dialog box Xilinx Development SystemX k = ∑ xmW N mk Xilinx LogiCOREXilinx Blocks Block Interface W N = eBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBlock Timing Figure 3-51 FFT Timing DiagramXilinx Blocks Xilinx LogiCORE Figure 3-52:FFT Timing CharacteristicsXilinx System Generator v2.1 Reference Guide Xilinx Development Systemyn = ∑ hixn –i Block InterfaceXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-53:FIR block parameters dialog box Xilinx Development SystemAccumulator MathMath Xilinx LogiCOREXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areBlock Parameters Dialog Box AddSubXilinx LogiCORE Xilinx BlocksBlock Parameters Dialog Box CMultXilinx System Generator v2.1 Reference Guide Figure 3-56:CMult block parameters dialog boxXilinx LogiCORE InverterXilinx Blocks MathBlock Parameters Dialog Box LogicalXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks Figure 3-58:Logical block parameters dialog boxBlock Parameters Dialog Box MultXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx LogiCORE Xilinx BlocksMath Relational NegateBlock Parameters Dialog Box Xilinx LogiCOREXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks MathShift ScaleBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box SineCosineXilinx Blocks Figure 3-64:Shift block parameters dialog boxXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the SineCosine block areLatency Using Block ThresholdXilinx Blocks Maximum CoreMATLAB I/O Enabled SubsystemsGateway Blocks Block Parameters Dialog BoxGateway In Enable AdapterMATLAB I/O Xilinx BlocksXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway In block areXilinx Development System Gateway Out Xilinx BlocksMATLAB I/O Xilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway Out block areXilinx Development System Clear Quantization Error Quantization Error BlocksQuantization Error DisplayDual Port RAM MemoryBlock Interface Xilinx System Generator v2.1 Reference GuideMemory Xilinx BlocksFigure 3-70:Illustration of write modes Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxParameters speciﬁc to the block are Xilinx Development SystemXilinx LogiCORE log 2dXilinx Blocks DepthBlock Parameters Dialog Box FIFOXilinx System Generator v2.1 Reference Guide Figure 3-72:FIFO block parameters dialog boxXilinx LogiCORE Xilinx BlocksMemory Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-73:ROM block parameters dialog box Xilinx Development Systemlog 2d Xilinx LogiCOREXilinx Blocks DepthBlock Interface Single Port RAMXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksMemory Xilinx System Generator v2.1 Reference Guide Figure 3-75:Illustration of write modesXilinx Development System log 2d Xilinx LogiCOREXilinx Blocks MemoryMealy State Machine State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks State MachineBlock Parameters Dialog Box Moore State MachineXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideFigure 3-80:Moore State Machine block diagram Xilinx BlocksState Machine Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-82:Construction of Next State and Output matrices Xilinx Development SystemXilinx LogiCORE Registered Mealy State MachineXilinx Blocks State MachineXilinx Development System Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Xilinx BlocksState Machine width = k + o N = depth × width = k + o2k + depth = 2k 2i = 2k +Xilinx LogiCORE Xilinx System Generator v2.1 Reference GuideRegistered Moore State Machine Xilinx BlocksState Machine Xilinx Development System Xilinx System Generator v2.1 Reference GuideN s = ds × ws = k 2k + ds = 2k 2i = 2k +Block Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Xilinx LogiCOREwhere Xilinx Development SystemUsing the System Generator installer Chapter System Generator Software FeaturesSystem Generator Software Features >>setupInstalled System Generator directory Using Black BoxesA Black Box Example Xilinx System Generator v2.1 Reference GuideBlack Box window Using Black BoxesSystem Generator Software Features Figure 4-1:Output of example black box functionIncorporating mixed language black boxes Use of mixed language projectsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUse of mixed language projects System Generator Software FeaturesFigure 4-2:Black Box block parameters dialog box Data Rate, Set ‘FAST’ Attribute Tips for creating a high performance designXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUsing the System Generator Constraints Files Using the System Generator Constraints FilesSystem Clock Period Multicycle Path ConstraintsExample for showing constraints use IOB Timing and Placement ConstraintsXilinx System Generator v2.1 Reference Guide Figure 4-4:Example of a multirate designUsing the System Generator Constraints Files System Generator Software FeaturesConstraints Files Important IssuesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features ∙sysgen.log - log ﬁle Xilinx System Generator v2.1 Reference GuideXilinx Development System Using the Xilinx Software Chapter Using the Xilinx SoftwareXilinx ISE 4.1i Project Navigator Opening a System Generator projectImplementing your design Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx ISE 4.1i Project Navigator Using the Xilinx SoftwareXilinx System Generator v2.1 Reference Guide Figure 5-6:Properties of simulation processXilinx Development System Using an EDIF software flow Using an EDIF software ﬂowSimulation Compiling your IPMXE libraries Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Demonstration designs Chapter Auxiliary FilesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemAuxiliary Files Perl scripts>> demo perl <scriptname> -hXilinx Development System Xilinx System Generator v2.1 Reference Guide