Xilinx System Generator v2.1 Reference Guide

Use of Xilinx Smart-IP Cores by the System Generator

To increase hardware performance, most System Generator blocks are implemented using Xilinx Smart-IP (Intellectual Property) LogiCOREs. These are hand crafted modules that make optimal use of FPGA resources to maximize performance. Some System Generator blocks map onto multiple LogiCOREs, for example, the 1024-point FFT, maps onto Dual Port Memory blocks as well as the FFT core itself.

Some Xilinx blocks also can be implemented as synthesizable VHDL modules, hence the LogiCORE is an option. When such a block cannot be implemented as a LogiCORE, System Generator automatically maps the block onto the synthesizable module. For example, the Xilinx Negate block generates a LogiCORE if you specify input of up to 256 bits, but for more than 256 bits the block is realized in synthesizable VHDL.

Many Xilinx blocks have implementations only as LogiCOREs. The reason for this is circuit performance. Because they are handcrafted for FPGA implementation, LogiCOREs have predictable performance in all design contexts. For example, the Xilinx FIR Filter block can be implemented only as the Distributed Arithmetic FIR Filter LogiCORE.

During algorithm exploration in Simulink and System Generator, it is common to iterate through block customization, Simulink simulation, and code generation. When you incorporate Black Box functionality, you can also add HDL simulation to this flow. To speed this design cycle, it is possible to instruct System Generator to not invoke Xilinx CORE Generator to re-generate LogiCOREs that have already been generated and have not changed. This can be done on individual blocks by the Generate Core checkbox control, or globally using the System Generator block parameters dialog box.

Licensed Cores

The System Generator targets a suite of new ready-to-use licensed LogiCORE algorithms for forward error correction (FEC), which are critical for detecting and correcting errors in wired and wireless communication systems during transmission of data to optimize the use of available bandwidth. The new algorithms include Reed- Solomon Encoder/ Decoder, a Viterbi Decoder, and an Interleaver/De-interleaver. These cores may be used for communication applications such as broadcast equipment, wireless LAN, cable modems, xDSL, satellite communications, microwave networks, and digital TV.

The System Generator allows you to build and simulate your FEC designs in Simulink using the Xilinx Blockset Communication library. System Generator creates a VHDL design and testbench that allows you to do a VHDL simulation of the FEC cores. Free evaluation versions of the FEC cores provide the behavioral models needed for VHDL simulation. The System Generator will allow you to generate the licensed core using the Xilinx CORE Generator after you have purchased and installed the FEC cores.

Licensing information, as well as instructions for downloading the cores, can be found at the Xilinx IP Center:

http://www.xilinx.com/ipcenter/fec_index.htm.

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Xilinx V2.1 manual Use of Xilinx Smart-IP Cores by the System Generator, Licensed Cores
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V2.1 specifications

Xilinx V2.1 is a notable iteration in the series of versatile and robust Field-Programmable Gate Arrays (FPGAs) developed to cater to a wide range of applications. Launched to provide enhancements in performance and flexibility, V2.1 embodies sophisticated technologies and features that stand out in the electronics industry.

One of the primary features of Xilinx V2.1 is its improved processing power. The architecture has been optimized to support higher clock speeds and increased logic density, allowing for more complex designs to be implemented effectively. This boost in performance is facilitated by utilizing advanced silicon technologies, which significantly reduce power consumption while maximizing efficiency.

Another significant characteristic of Xilinx V2.1 is its enhanced I/O (Input/Output) capabilities. The device supports a variety of industry-standard interfaces, which include PCI Express, SATA, and various serial communication protocols. Such adaptability ensures seamless integration into existing systems, providing engineers with the flexibility to adapt to various application requirements without the need for substantial redesign efforts.

Xilinx V2.1 also features improved scalability, making it a prime choice for applications that demand diverse performance levels. This device supports an array of configurations and can be used in small-scale projects as well as in larger, more demanding environments requiring extensive resources. This scalability is further aided by support for multiple development platforms, enabling rapid prototyping and simplifying the design process.

Security is increasingly becoming a priority in digital design, and Xilinx V2.1 addresses this concern via hardware security features. It includes enhanced encryption protocols and secure boot functionalities, which help protect intellectual property and sensitive data from unauthorized access.

Additionally, the integration of advanced DSP (Digital Signal Processing) blocks allows Xilinx V2.1 to efficiently handle data-intensive tasks such as video processing and real-time signal analysis. These capabilities make it suitable for applications in telecommunications, automotive systems, and industrial automation.

Xilinx V2.1 also benefits from a rich development environment, including robust software tools that facilitate design entry, simulation, and verification. The support for industry-standard programming languages like VHDL and Verilog simplifies the development process, enabling engineers to design complex systems more efficiently.

In summary, Xilinx V2.1 stands out due to its impressive combination of high performance, flexibility, scalability, security, and comprehensive development support. These features make it a valuable asset for engineers and developers looking to innovate across various sectors, from telecommunications and automotive to industrial applications.
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