Xilinx System Generator v2.1 Reference Guide
vlog<file>
line for each Verilog wrapper that is listed in the verilogFiles file, another file produced by System Generator. The vsim line in the vsim.do file needs to be augmented by adding a
suffix.
Tips for creating a high performance design
The following are suggestions for some design practices in System Generator that will translate to an efficient and high performance design in your FPGA.
∙Register inputs and outputs of your design. This can be done by placing a Delay block with a latency of 1 or a Register block after the Gateway In blocks and before the Gateway Out blocks. Selecting any of the Register block features will add extra logic. For example if the Store Only Valid Data option is selected on the Register block, one level of logic will be added to the clock enable path.
∙Double registering the I/Os may also be beneficial. This can be performed by instantiating two separate Register blocks, or by instantiating two Delay blocks with latency of 1. This will allow one of the registers to be packed into the IOB and the other to be placed next to the logic in the FPGA fabric. A Delay block with latency set to 2 will not give the same results since this block is implemented using a SRL16 and cannot be packed into an IOB.
∙Use the IOB Timing Constraint option:
Data Rate, Set ‘FAST’ Attribute
on all Gateway In and Gateway Out blocks. When this attribute is selected on the Gateway blocks, the IOB delay is reduced, but the IO noise and power consumption increases.
∙In general it is important to insert pipeline registers wherever possible. Deep pipelines are efficiently implemented with the Delay blocks since the SRL16 primitive is used. If an initial value is needed on a register, the Register block supplies this functionality. In addition, the Sync block in the Xilinx Blockset Basic Elements library can help with retiming your design. The Color Space Conversion demo provides an example of this. (This demo, as well as others, can be found through the MATLAB Demos or by typing demo at the MATLAB console prompt.)
∙Up and down samplers have combinational feedthroughs. Whenever possible, place a register on the output of a sample rate converter. The Xilinx blocks Up Sample and Down Sample (in the Xilinx Blockset Basic Elements library) provide more information.
∙Saturation arithmetic and rounding have area and performance costs. Use only if necessary.
∙Use global port selections only if necessary. On the System Generator block parameters dialog box, only select the Create Global Clock Enable Port or Create Global Clear Port options if absolutely necessary. Global clock
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