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Xilinx V2.1 manual Xilinx System Generator v2.1 Reference Guide, Xilinx Development System

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Xilinx System Generator v2.1 Reference Guide

stream of bits. The state transition diagram and equivalent transition table are shown below.

Figure 3-85: Registered Mealy State Machine example transition diagram and table

The table lists the next state and output that result from the current state and input. For instance, if the current state is 3 and the input is 1, the next state is 1 and the output is 1, indicating the detection of the desired sequence.

120	Xilinx Development System

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Xilinx V2.1 manual Xilinx System Generator v2.1 Reference Guide, Xilinx Development System

Contents

Printed in U.S.A Xilinx Blocks System Generator Software FeaturesUsing the Xilinx Software Auxiliary Files Xilinx System Generator v2.1 forManual Contents About This ManualXilinx System Generator v2.1 Reference Guide Xilinx Development SystemAdditional Resources ResourceDescription/URL Conventions Typographical>> cd <your $MATLAB home directory> Xilinx System Generator v2.1 Reference GuideContents ChapterIntroduction Chapter 2 Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter 4 System Generator Software Features Chapter 5 Using the Xilinx SoftwareChapter 6 Auxiliary Files Chapter Introduction Industry and Product OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator System Level Modeling with System GeneratorIntroduction System GeneratorThe System Generator Design Flow Xilinx System Generator v2.1 Reference GuideXilinx Development System The System Generator Design Flow LibraryMATLAB Environment SimulinkArithmetic Data Types Xilinx System Generator v2.1 Reference GuideXilinx Development System Hardware Handshaking Multirate SystemsHardware Handshaking IntroductionBit-Trueand Cycle-TrueModeling Automatic Testbench GenerationXilinx System Generator v2.1 Reference Guide Xilinx Development SystemWhat is a Xilinx Block? What is a Xilinx Block?Chapter Xilinx Blockset Overview Xilinx Blockset OverviewThe Nature of Signals in the Xilinx Blockset The Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemThe Nature of Signals in the Xilinx Blockset Valid and Invalid DataPort Data Types Xilinx Blockset OverviewLicensed Cores Xilinx System Generator v2.1 Reference GuideXilinx Development System Common Options in Block Parameters Dialog Box Xilinx LogiCORE VersionsCommon Options in Block Parameters Dialog Box Xilinx Blockset OverviewUse Placement Information for Core Arithmetic TypeImplement with Xilinx Smart-IP Core if possible Generate CorePrecision Number of BitsOverﬂow and Quantization Override with DoublesSample Period Use Explicit Sample PeriodXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter Xilinx Blocks Basic ElementsSystem Generator Xilinx BlocksBlock Parameters Dialog Box ∙Xilinx Product Family∙Target Directory ∙System Clock Period∙Global Clock Enable and Global Clear ∙Override with Doubles∙Generate Cores ∙Generate buttonAddressable Shift Register Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlack Box Incorporating mixed language black boxesBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Figure 3-3:Black Box block parameters dialog boxBasic Elements Concat Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideConstant ConvertBlock Parameters Dialog Box Xilinx BlocksCounter Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-7:Convert block parameters dialog boxXilinx Blocks Basic ElementsBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-8:Counter block parameters dialog box Xilinx Development SystemDelay Xilinx LogiCOREBlock Parameters Dialog Box Xilinx BlocksDown Sample Xilinx System Generator v2.1 Reference GuideFigure 3-11:Down sample circuit behavior Xilinx Development SystemGet Valid Bit Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Figure 3-13:Mux block parameters dialog boxParallel to Serial Block InterfaceXilinx Blocks Basic ElementsRegister Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Interface Block Parameters Dialog BoxXilinx Blocks Figure 3-16:Register block parameters dialog boxReinterpret Xilinx System Generator v2.1 Reference GuideXilinx Development System Serial to Parallel Block Parameters Dialog boxXilinx Blocks Basic ElementsBlock Interface Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areSet Valid Bit SliceBlock Parameters Dialog Box Xilinx BlocksBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-21:Slice block operation Xilinx Development SystemSync Xilinx BlocksBasic Elements Xilinx System Generator v2.1 Reference Guide Figure 3-23:Sync block useXilinx Development System Block Parameters Dialog Box Xilinx BlocksFigure 3-26:Sync block parameters dialog box Basic ElementsUp Sample Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Parameters Dialog Box Xilinx BlocksFigure 3-29:Up Sample block parameters dialog box Basic ElementsCommunication Convolutional EncoderBlock Interface Xilinx System Generator v2.1 Reference GuideCommunication Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksDepuncture Xilinx System Generator v2.1 Reference GuideFigure 3-32:Example of Depuncture block use Xilinx Development SystemInterleaver Deinterleaver Block Parameters Dialog BoxXilinx Blocks CommunicationXilinx System Generator v2.1 Reference Guide Figure 3-34:Forney convolutional interleaver with a constant difference between consecutive branchesXilinx Development System Block Interface Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksPuncture Xilinx System Generator v2.1 Reference GuideXilinx Development System RS Decoder Block Parameters Dialog BoxXilinx Blocks Figure 3-38:Puncture block parameters dialog boxBlock Interface Xilinx System Generator v2.1 Reference GuideThe port descriptions are Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksCommunication g x = ∏ x –ahxGS + i i = Xilinx System Generator v2.1 Reference GuideXilinx Development System RS Encoder LatencyXilinx LogiCore Xilinx Blocksg x = x –ai x –ai + 1 . . . . x –ai + 2t c x = g x ⋅ ig x = x –a0 x –a1 x –a2 . . . . x –a15 Xilinx System Generator v2.1 Reference GuideBlock Interface Xilinx BlocksCommunication Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the RS Encoder block are Xilinx Development Systemg x = ∏ x –ahxGS + i i = Xilinx BlocksCommunication Viterbi Decoder LatencyXilinx LogiCore Xilinx System Generator v2.1 Reference GuideBlock Interface Block Parameters Dialog BoxCommunication Xilinx LogiCore Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Interface Xilinx BlocksFigure 3-46:Pipelined decimator and interpolator Block Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Figure 3-47:CIC block parameters dialog boxXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-49:DDS block parameters dialog box Xilinx Development SystemX k = ∑ xmW N mk Xilinx LogiCOREXilinx Blocks W N = e Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBlock Timing Figure 3-51 FFT Timing DiagramXilinx Blocks Figure 3-52:FFT Timing Characteristics Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Xilinx Development Systemyn = ∑ hixn –i Block InterfaceXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-53:FIR block parameters dialog box Xilinx Development SystemMath AccumulatorMath Xilinx LogiCOREBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areAddSub Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksCMult Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-56:CMult block parameters dialog boxInverter Xilinx LogiCOREXilinx Blocks MathLogical Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks Figure 3-58:Logical block parameters dialog boxMult Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx LogiCORE Xilinx BlocksMath Negate RelationalBlock Parameters Dialog Box Xilinx LogiCOREBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks MathScale ShiftBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideSineCosine Block Parameters Dialog BoxXilinx Blocks Figure 3-64:Shift block parameters dialog boxBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the SineCosine block areThreshold Latency Using BlockXilinx Blocks Maximum CoreEnabled Subsystems MATLAB I/OGateway Blocks Block Parameters Dialog BoxEnable Adapter Gateway InMATLAB I/O Xilinx BlocksXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway In block areXilinx Development System Gateway Out Xilinx BlocksMATLAB I/O Xilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway Out block areXilinx Development System Quantization Error Blocks Clear Quantization ErrorQuantization Error DisplayMemory Dual Port RAMBlock Interface Xilinx System Generator v2.1 Reference GuideMemory Xilinx BlocksFigure 3-70:Illustration of write modes Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the block are Xilinx Development Systemlog 2d Xilinx LogiCOREXilinx Blocks DepthFIFO Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-72:FIFO block parameters dialog boxXilinx LogiCORE Xilinx BlocksMemory Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-73:ROM block parameters dialog box Xilinx Development SystemXilinx LogiCORE log 2dXilinx Blocks DepthSingle Port RAM Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksMemory Xilinx System Generator v2.1 Reference Guide Figure 3-75:Illustration of write modesXilinx Development System Xilinx LogiCORE log 2dXilinx Blocks MemoryState Machine Mealy State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemState Machine Xilinx BlocksMoore State Machine Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideFigure 3-80:Moore State Machine block diagram Xilinx BlocksState Machine Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-82:Construction of Next State and Output matrices Xilinx Development SystemRegistered Mealy State Machine Xilinx LogiCOREXilinx Blocks State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksState Machine depth = 2k 2i = 2k + width = k + o N = depth × width = k + o2k +Xilinx LogiCORE Xilinx System Generator v2.1 Reference GuideRegistered Moore State Machine Xilinx BlocksState Machine Xilinx System Generator v2.1 Reference Guide Xilinx Development Systemds = 2k 2i = 2k + N s = ds × ws = k 2k +Block Parameters Dialog Box Xilinx BlocksXilinx LogiCORE Xilinx System Generator v2.1 Reference Guidewhere Xilinx Development SystemChapter System Generator Software Features Using the System Generator installerSystem Generator Software Features >>setupUsing Black Boxes Installed System Generator directoryA Black Box Example Xilinx System Generator v2.1 Reference GuideUsing Black Boxes Black Box windowSystem Generator Software Features Figure 4-1:Output of example black box functionUse of mixed language projects Incorporating mixed language black boxesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUse of mixed language projects System Generator Software FeaturesFigure 4-2:Black Box block parameters dialog box Tips for creating a high performance design Data Rate, Set ‘FAST’ AttributeXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUsing the System Generator Constraints Files Using the System Generator Constraints FilesSystem Clock Period Multicycle Path ConstraintsIOB Timing and Placement Constraints Example for showing constraints useXilinx System Generator v2.1 Reference Guide Figure 4-4:Example of a multirate designSystem Generator Software Features Using the System Generator Constraints FilesImportant Issues Constraints FilesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features ∙sysgen.log - log ﬁle Xilinx System Generator v2.1 Reference GuideXilinx Development System Chapter Using the Xilinx Software Using the Xilinx SoftwareXilinx ISE 4.1i Project Navigator Opening a System Generator projectImplementing your design Xilinx System Generator v2.1 Reference GuideXilinx Development System Using the Xilinx Software Xilinx ISE 4.1i Project NavigatorXilinx System Generator v2.1 Reference Guide Figure 5-6:Properties of simulation processXilinx Development System Using an EDIF software ﬂow Using an EDIF software flowSimulation Compiling your IPMXE libraries Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Chapter Auxiliary Files Demonstration designsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemPerl scripts Auxiliary Files>> demo perl <scriptname> -hXilinx System Generator v2.1 Reference Guide Xilinx Development System