Xilinx V2.1 manual Fft

Xilinx Blocks

∙Phase Increment Type: specifies Δθ to be either constant or register. Choice of register activates optional ports on the block.

∙Phase Increment: specifies value of phase increment constant, a multiple of 2π. The number of bits is determined in one of two ways. If the increment type is Register, the number of bits is set to the width of the data port. If the increment type is Constant, the number of bits is inferred from the phase increment value.

∙Accumulator Latency: specifies the latency in the phase accumulator to be zero or one.

∙Accumulator Width: specifies the phase accumulator width; value must be between 3 and 32 inclusive.

∙Phase Offset Type: specifies phase offset to be Constant, Register, or None. Choice of register activates optional ports on the block.

∙Phase Offset: specifies value of phase offset constant, as a multiple of 2π. The number of bits is determined in one of two ways. If the offset type is Register, the number of bits is set to the width of the data port. If the offset type is Constant, the number of bits is inferred from the phase offset value.

∙Memory Type: directs the block to be implemented either with distributed or block RAM.

∙Use Phase Dithering: when checked, a dither sequence is added to the result of the phase accumulator.

∙Pipeline the DDS: when checked, the implementation is fully pipelined.

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The DDS block always uses the Xilinx LogiCORE DDS v4.0.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\dds_v4_0\doc\dds

.pdf

FFT

The Xilinx FFT Block computes the Discrete Fourier Transform (DFT) using the radix-4 Cooley-Tukey algorithm, explained below:

The N-point DFT of a complex vector x(n) = [x(0), x(1), ..., x(N-1)], is the vector X(k) = [X(0), X(1), ..., X(N-1)], where the k-th element

N–1

X (k ) = ∑ x(m)W N mk

m = 0

DSP 75