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Xilinx V2.1 Memory, Dual Port RAM, Block Interface, Xilinx System Generator v2.1 Reference Guide

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Memory

Xilinx System Generator v2.1 Reference Guide

Memory

This section contains Xilinx blocks that use Xilinx memory LogiCOREs.

Dual Port RAM

The Xilinx Dual Port RAM block implements a random access memory (RAM).

Block Interface

The block has two independent sets of ports for simultaneous reading and writing. Each port set has one output port and three input ports for address, input data, and write enable (WE). The Dual Port RAM block supports various Form Factors,

FF = WB / WA where WB is data width of Port B and WA is Data Width of Port A.

The Dual port RAM block allows FF of 1, 2, 4, 8, 16 for Virtex and 1, 2, 4, 8, 16 or 32 for Virtex-II device families, provided that:

Mod [ ( DA x WA ) , WB] = 0 for a given FF

where

DA : Depth speciﬁed for Port A

The Depth of port B (DB) is inferred from the speciﬁed form factor as follows: DB = DA / FF.

The data input ports on Port A and B can have different arithmetic type and binary point position for a form factor of 1. For form factors greater than 1, the data input ports on Port A and Port B should have an unsigned arithmetic type with binary point at 0. The output ports, labeled A and B, have the same types as the corresponding input data ports.

The location in the memory block can be accessed for reading or writing by providing the valid address on each individual address port. A valid address is an unsigned integer from 0 to d-1, where d denotes the RAM depth (number of words in the RAM) for the particular port. An attempt to read past the end of the memory is caught as an error in simulation. The initial RAM contents can be speciﬁed through a block parameter. Each write enable port must be a 1-bit unsigned integer. When the WE port is 1, the value on the data input is written to the location indicated by the address line.

The output during a write operation depends on the write mode. When the WE is 0, the output port has the value at the location speciﬁed by the address line. Write contention results in data being not written to the memory location and the corresponding outputs are ﬂagged as invalid. During a write operation (WE asserted), the data presented on the input data port is stored in memory at the location selected

102	Xilinx Development System

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Xilinx V2.1 manual Memory, Dual Port RAM, Block Interface, Xilinx System Generator v2.1 Reference Guide

Contents

Using the Xilinx Software Auxiliary Files Printed in U.S.AXilinx Blocks System Generator Software Features Xilinx System Generator v2.1 forXilinx System Generator v2.1 Reference Guide Manual ContentsAbout This Manual Xilinx Development SystemAdditional Resources ResourceDescription/URL >> cd <your $MATLAB home directory> ConventionsTypographical Xilinx System Generator v2.1 Reference GuideIntroduction ContentsChapter Chapter 2 Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter 4 System Generator Software Features Chapter 5 Using the Xilinx SoftwareChapter 6 Auxiliary Files Xilinx System Generator v2.1 Reference Guide Chapter IntroductionIndustry and Product Overview Xilinx Development SystemIntroduction System GeneratorSystem Level Modeling with System Generator System GeneratorThe System Generator Design Flow Xilinx System Generator v2.1 Reference GuideXilinx Development System MATLAB Environment The System Generator Design FlowLibrary SimulinkArithmetic Data Types Xilinx System Generator v2.1 Reference GuideXilinx Development System Hardware Handshaking Hardware HandshakingMultirate Systems IntroductionXilinx System Generator v2.1 Reference Guide Bit-Trueand Cycle-TrueModelingAutomatic Testbench Generation Xilinx Development SystemChapter Xilinx Blockset Overview What is a Xilinx Block?What is a Xilinx Block? Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide The Nature of Signals in the Xilinx BlocksetThe Block Parameters Dialog Box Xilinx Development SystemPort Data Types The Nature of Signals in the Xilinx BlocksetValid and Invalid Data Xilinx Blockset OverviewLicensed Cores Xilinx System Generator v2.1 Reference GuideXilinx Development System Common Options in Block Parameters Dialog Box Common Options in Block Parameters Dialog BoxXilinx LogiCORE Versions Xilinx Blockset OverviewImplement with Xilinx Smart-IP Core if possible Use Placement Information for CoreArithmetic Type Generate CoreOverﬂow and Quantization PrecisionNumber of Bits Override with DoublesXilinx System Generator v2.1 Reference Guide Sample PeriodUse Explicit Sample Period Xilinx Development SystemSystem Generator Chapter Xilinx BlocksBasic Elements Xilinx Blocks∙Target Directory Block Parameters Dialog Box∙Xilinx Product Family ∙System Clock Period∙Generate Cores ∙Global Clock Enable and Global Clear∙Override with Doubles ∙Generate buttonXilinx System Generator v2.1 Reference Guide Addressable Shift RegisterBlock Interface Xilinx Development SystemXilinx Blocks Xilinx LogiCOREBlock Parameters Dialog Box Basic ElementsBlock Parameters Dialog Box Black BoxIncorporating mixed language black boxes Xilinx System Generator v2.1 Reference GuideXilinx Blocks Figure 3-3:Black Box block parameters dialog boxBasic Elements Block Parameters Dialog Box ConcatBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box ConstantConvert Xilinx BlocksXilinx System Generator v2.1 Reference Guide CounterBlock Parameters Dialog Box Figure 3-7:Convert block parameters dialog boxXilinx Blocks Basic ElementsFigure 3-8:Counter block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box DelayXilinx LogiCORE Xilinx BlocksFigure 3-11:Down sample circuit behavior Down SampleXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Get Valid BitBlock Parameters Dialog Box Basic ElementsXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-13:Mux block parameters dialog boxXilinx Blocks Parallel to SerialBlock Interface Basic ElementsXilinx System Generator v2.1 Reference Guide RegisterBlock Parameters Dialog Box Xilinx Development SystemXilinx Blocks Block InterfaceBlock Parameters Dialog Box Figure 3-16:Register block parameters dialog boxReinterpret Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Serial to ParallelBlock Parameters Dialog box Basic ElementsXilinx System Generator v2.1 Reference Guide Block InterfaceBlock Parameters Dialog Box Parameters speciﬁc to the block areBlock Parameters Dialog Box Set Valid BitSlice Xilinx BlocksFigure 3-21:Slice block operation Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSync Xilinx BlocksBasic Elements Xilinx System Generator v2.1 Reference Guide Figure 3-23:Sync block useXilinx Development System Figure 3-26:Sync block parameters dialog box Block Parameters Dialog BoxXilinx Blocks Basic ElementsUp Sample Xilinx System Generator v2.1 Reference GuideXilinx Development System Figure 3-29:Up Sample block parameters dialog box Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlock Interface CommunicationConvolutional Encoder Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE CommunicationBlock Parameters Dialog Box Xilinx BlocksFigure 3-32:Example of Depuncture block use DepunctureXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Interleaver DeinterleaverBlock Parameters Dialog Box CommunicationXilinx System Generator v2.1 Reference Guide Figure 3-34:Forney convolutional interleaver with a constant difference between consecutive branchesXilinx Development System Xilinx LogiCORE Block InterfaceBlock Parameters Dialog Box Xilinx BlocksPuncture Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks RS DecoderBlock Parameters Dialog Box Figure 3-38:Puncture block parameters dialog boxThe port descriptions are Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksCommunication g x = ∏ x –ahxGS + i i = Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx LogiCore RS EncoderLatency Xilinx Blocksg x = x –a0 x –a1 x –a2 . . . . x –a15 g x = x –ai x –ai + 1 . . . . x –ai + 2tc x = g x ⋅ i Xilinx System Generator v2.1 Reference GuideBlock Interface Xilinx BlocksCommunication Parameters speciﬁc to the RS Encoder block are Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development Systemg x = ∏ x –ahxGS + i i = Xilinx BlocksCommunication Xilinx LogiCore Viterbi DecoderLatency Xilinx System Generator v2.1 Reference GuideBlock Interface Block Parameters Dialog BoxCommunication Xilinx LogiCore Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Interface Xilinx BlocksFigure 3-46:Pipelined decimator and interpolator Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-47:CIC block parameters dialog boxXilinx Blocks Figure 3-49:DDS block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemX k = ∑ xmW N mk Xilinx LogiCOREXilinx Blocks Block Parameters Dialog Box W N = eBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Timing Figure 3-51 FFT Timing DiagramXilinx Blocks Xilinx System Generator v2.1 Reference Guide Figure 3-52:FFT Timing CharacteristicsXilinx LogiCORE Xilinx Development Systemyn = ∑ hixn –i Block InterfaceXilinx Blocks Figure 3-53:FIR block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemMath MathAccumulator Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Parameters speciﬁc to the block areXilinx LogiCORE AddSubBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide CMultBlock Parameters Dialog Box Figure 3-56:CMult block parameters dialog boxXilinx Blocks InverterXilinx LogiCORE MathXilinx LogiCORE LogicalBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block Parameters Dialog BoxXilinx LogiCORE Figure 3-58:Logical block parameters dialog boxXilinx System Generator v2.1 Reference Guide MultBlock Parameters Dialog Box Xilinx Development SystemXilinx LogiCORE Xilinx BlocksMath Block Parameters Dialog Box NegateRelational Xilinx LogiCOREXilinx Blocks Block Parameters Dialog BoxXilinx LogiCORE MathBlock Parameters Dialog Box ScaleShift Xilinx System Generator v2.1 Reference GuideXilinx Blocks SineCosineBlock Parameters Dialog Box Figure 3-64:Shift block parameters dialog boxXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Parameters speciﬁc to the SineCosine block areXilinx Blocks ThresholdLatency Using Block Maximum CoreGateway Blocks Enabled SubsystemsMATLAB I/O Block Parameters Dialog BoxMATLAB I/O Enable AdapterGateway In Xilinx BlocksXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway In block areXilinx Development System Gateway Out Xilinx BlocksMATLAB I/O Xilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway Out block areXilinx Development System Quantization Error Quantization Error BlocksClear Quantization Error DisplayBlock Interface MemoryDual Port RAM Xilinx System Generator v2.1 Reference GuideMemory Xilinx BlocksFigure 3-70:Illustration of write modes Parameters speciﬁc to the block are Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks log 2dXilinx LogiCORE DepthXilinx System Generator v2.1 Reference Guide FIFOBlock Parameters Dialog Box Figure 3-72:FIFO block parameters dialog boxXilinx LogiCORE Xilinx BlocksMemory Figure 3-73:ROM block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Xilinx LogiCORElog 2d DepthXilinx System Generator v2.1 Reference Guide Single Port RAMBlock Interface Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksMemory Xilinx System Generator v2.1 Reference Guide Figure 3-75:Illustration of write modesXilinx Development System Xilinx Blocks Xilinx LogiCORElog 2d MemoryXilinx System Generator v2.1 Reference Guide State MachineMealy State Machine Xilinx Development SystemState Machine Xilinx BlocksXilinx LogiCORE Moore State MachineBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-80:Moore State Machine block diagram Xilinx BlocksState Machine Figure 3-82:Construction of Next State and Output matrices Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Registered Mealy State MachineXilinx LogiCORE State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx BlocksState Machine Xilinx LogiCORE depth = 2k 2i = 2k +width = k + o N = depth × width = k + o2k + Xilinx System Generator v2.1 Reference GuideRegistered Moore State Machine Xilinx BlocksState Machine Xilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box ds = 2k 2i = 2k +N s = ds × ws = k 2k + Xilinx Blockswhere Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Chapter System Generator Software FeaturesUsing the System Generator installer >>setupA Black Box Example Using Black BoxesInstalled System Generator directory Xilinx System Generator v2.1 Reference GuideSystem Generator Software Features Using Black BoxesBlack Box window Figure 4-1:Output of example black box functionXilinx System Generator v2.1 Reference Guide Use of mixed language projectsIncorporating mixed language black boxes Xilinx Development SystemUse of mixed language projects System Generator Software FeaturesFigure 4-2:Black Box block parameters dialog box Xilinx System Generator v2.1 Reference Guide Tips for creating a high performance designData Rate, Set ‘FAST’ Attribute Xilinx Development SystemSystem Clock Period Using the System Generator Constraints FilesUsing the System Generator Constraints Files Multicycle Path ConstraintsXilinx System Generator v2.1 Reference Guide IOB Timing and Placement ConstraintsExample for showing constraints use Figure 4-4:Example of a multirate designSystem Generator Software Features Using the System Generator Constraints FilesXilinx System Generator v2.1 Reference Guide Important IssuesConstraints Files Xilinx Development SystemFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features ∙sysgen.log - log ﬁle Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx ISE 4.1i Project Navigator Chapter Using the Xilinx SoftwareUsing the Xilinx Software Opening a System Generator projectImplementing your design Xilinx System Generator v2.1 Reference GuideXilinx Development System Using the Xilinx Software Xilinx ISE 4.1i Project NavigatorXilinx System Generator v2.1 Reference Guide Figure 5-6:Properties of simulation processXilinx Development System Simulation Using an EDIF software ﬂowUsing an EDIF software flow Compiling your IPMXE libraries Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Xilinx System Generator v2.1 Reference Guide Chapter Auxiliary FilesDemonstration designs Xilinx Development System>> demo Perl scriptsAuxiliary Files perl <scriptname> -hXilinx System Generator v2.1 Reference Guide Xilinx Development System