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Xilinx V2.1 Block Parameters Dialog Box, Xilinx LogiCORE, Parameters speciﬁc to the block are

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Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-54: Accumulator block parameters dialog box

Parameters speciﬁc to the block are:

∙Number of Bits (output width): speciﬁes the output width which must match the input width. If the data input does not match the output width, an error is reported.

∙Overflow: speciﬁes behavior on internal overﬂow to be Wrap, Saturate, or ﬂag as an Error.

∙Operation: This is a list of two choices: add and subtract. This determines whether the block is adder or subtractor based.

∙Feedback Scaling: speciﬁes the feedback scale factor to be one of the following:

1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, or 1/256.

∙Reset to input: when selected, the output of the accumulator is loaded by the data on input port b whenever the accumulator is reset. When not selected, the output of the accumulator is reset to 0.

The type of the output is the same as that of the input. The block always has a latency of 1.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE Accumulator V5.0. The data width must be between 1 and 258, inclusive.

The Core datasheet can be found on your local disk at:

82	Xilinx Development System

Image 82

Xilinx V2.1 manual Block Parameters Dialog Box, Xilinx LogiCORE, Xilinx System Generator v2.1 Reference Guide

Contents

Using the Xilinx Software Auxiliary Files Printed in U.S.AXilinx Blocks System Generator Software Features Xilinx System Generator v2.1 forXilinx System Generator v2.1 Reference Guide Manual ContentsAbout This Manual Xilinx Development SystemResource Additional ResourcesDescription/URL >> cd <your $MATLAB home directory> ConventionsTypographical Xilinx System Generator v2.1 Reference GuideIntroduction ContentsChapter Chapter 2 Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter 5 Using the Xilinx Software Chapter 4 System Generator Software FeaturesChapter 6 Auxiliary Files Xilinx System Generator v2.1 Reference Guide Chapter IntroductionIndustry and Product Overview Xilinx Development SystemIntroduction System GeneratorSystem Level Modeling with System Generator System GeneratorXilinx System Generator v2.1 Reference Guide The System Generator Design FlowXilinx Development System MATLAB Environment The System Generator Design FlowLibrary SimulinkXilinx System Generator v2.1 Reference Guide Arithmetic Data TypesXilinx Development System Hardware Handshaking Hardware HandshakingMultirate Systems IntroductionXilinx System Generator v2.1 Reference Guide Bit-Trueand Cycle-TrueModelingAutomatic Testbench Generation Xilinx Development SystemChapter Xilinx Blockset Overview What is a Xilinx Block?What is a Xilinx Block? Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide The Nature of Signals in the Xilinx BlocksetThe Block Parameters Dialog Box Xilinx Development SystemPort Data Types The Nature of Signals in the Xilinx BlocksetValid and Invalid Data Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Licensed CoresXilinx Development System Common Options in Block Parameters Dialog Box Common Options in Block Parameters Dialog BoxXilinx LogiCORE Versions Xilinx Blockset OverviewImplement with Xilinx Smart-IP Core if possible Use Placement Information for CoreArithmetic Type Generate CoreOverﬂow and Quantization PrecisionNumber of Bits Override with DoublesXilinx System Generator v2.1 Reference Guide Sample PeriodUse Explicit Sample Period Xilinx Development SystemSystem Generator Chapter Xilinx BlocksBasic Elements Xilinx Blocks∙Target Directory Block Parameters Dialog Box∙Xilinx Product Family ∙System Clock Period∙Generate Cores ∙Global Clock Enable and Global Clear∙Override with Doubles ∙Generate buttonXilinx System Generator v2.1 Reference Guide Addressable Shift RegisterBlock Interface Xilinx Development SystemXilinx Blocks Xilinx LogiCOREBlock Parameters Dialog Box Basic ElementsBlock Parameters Dialog Box Black BoxIncorporating mixed language black boxes Xilinx System Generator v2.1 Reference GuideFigure 3-3:Black Box block parameters dialog box Xilinx BlocksBasic Elements Block Parameters Dialog Box ConcatBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box ConstantConvert Xilinx BlocksXilinx System Generator v2.1 Reference Guide CounterBlock Parameters Dialog Box Figure 3-7:Convert block parameters dialog boxXilinx Blocks Basic ElementsFigure 3-8:Counter block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box DelayXilinx LogiCORE Xilinx BlocksFigure 3-11:Down sample circuit behavior Down SampleXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Get Valid BitBlock Parameters Dialog Box Basic ElementsXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-13:Mux block parameters dialog boxXilinx Blocks Parallel to SerialBlock Interface Basic ElementsXilinx System Generator v2.1 Reference Guide RegisterBlock Parameters Dialog Box Xilinx Development SystemXilinx Blocks Block InterfaceBlock Parameters Dialog Box Figure 3-16:Register block parameters dialog boxXilinx System Generator v2.1 Reference Guide ReinterpretXilinx Development System Xilinx Blocks Serial to ParallelBlock Parameters Dialog box Basic ElementsXilinx System Generator v2.1 Reference Guide Block InterfaceBlock Parameters Dialog Box Parameters speciﬁc to the block areBlock Parameters Dialog Box Set Valid BitSlice Xilinx BlocksFigure 3-21:Slice block operation Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development 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Dialog Box Block InterfaceCommunication Xilinx System Generator v2.1 Reference Guide Xilinx LogiCoreXilinx Development System Xilinx Blocks Block InterfaceFigure 3-46:Pipelined decimator and interpolator Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-47:CIC block parameters dialog boxXilinx Blocks Figure 3-49:DDS block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx LogiCORE X k = ∑ xmW N mkXilinx Blocks Block Parameters Dialog Box W N = eBlock Interface Xilinx System Generator v2.1 Reference GuideFigure 3-51 FFT Timing Diagram Block TimingXilinx Blocks Xilinx System Generator v2.1 Reference Guide Figure 3-52:FFT Timing CharacteristicsXilinx LogiCORE Xilinx Development SystemBlock Interface yn = ∑ hixn –iXilinx Blocks Figure 3-53:FIR block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development 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3-64:Shift block parameters dialog boxXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Parameters speciﬁc to the SineCosine block areXilinx Blocks ThresholdLatency Using Block Maximum CoreGateway Blocks Enabled SubsystemsMATLAB I/O Block Parameters Dialog BoxMATLAB I/O Enable AdapterGateway In Xilinx BlocksParameters speciﬁc to the Gateway In block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Gateway OutMATLAB I/O Parameters speciﬁc to the Gateway Out block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Quantization Error Quantization Error BlocksClear Quantization Error DisplayBlock Interface MemoryDual Port RAM Xilinx System Generator v2.1 Reference GuideXilinx Blocks MemoryFigure 3-70:Illustration of write modes Parameters speciﬁc to the block are Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks log 2dXilinx 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State and Output matrices Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Registered Mealy State MachineXilinx LogiCORE State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxState Machine Xilinx LogiCORE depth = 2k 2i = 2k +width = k + o N = depth × width = k + o2k + Xilinx System Generator v2.1 Reference GuideXilinx Blocks Registered Moore State MachineState Machine Xilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box ds = 2k 2i = 2k +N s = ds × ws = k 2k + Xilinx Blockswhere Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Chapter System Generator Software FeaturesUsing the System Generator installer >>setupA Black Box Example Using Black BoxesInstalled System Generator directory Xilinx System Generator v2.1 Reference GuideSystem Generator Software Features Using Black BoxesBlack Box window Figure 4-1:Output of example black box functionXilinx System Generator v2.1 Reference Guide Use of mixed language projectsIncorporating mixed language black boxes Xilinx Development SystemSystem Generator Software Features Use of mixed language projectsFigure 4-2:Black Box block parameters dialog box Xilinx System Generator v2.1 Reference Guide Tips for creating a high performance designData Rate, Set ‘FAST’ Attribute Xilinx Development SystemSystem Clock Period Using the System Generator Constraints FilesUsing the System Generator Constraints Files Multicycle Path ConstraintsXilinx System Generator v2.1 Reference Guide IOB Timing and Placement ConstraintsExample for showing constraints use Figure 4-4:Example of a multirate designSystem Generator Software Features Using the System Generator Constraints FilesXilinx System Generator v2.1 Reference Guide Important IssuesConstraints Files Xilinx Development SystemFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features Xilinx System Generator v2.1 Reference Guide ∙sysgen.log - log ﬁleXilinx Development System Xilinx ISE 4.1i Project Navigator Chapter Using the Xilinx SoftwareUsing the Xilinx Software Opening a System Generator projectXilinx System Generator v2.1 Reference Guide Implementing your designXilinx Development System Using the Xilinx Software Xilinx ISE 4.1i Project NavigatorFigure 5-6:Properties of simulation process Xilinx System Generator v2.1 Reference GuideXilinx Development System Simulation Using an EDIF software ﬂowUsing an EDIF software flow Compiling your IPXilinx System Generator v2.1 Reference Guide MXE librariesXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Xilinx System Generator v2.1 Reference Guide Chapter Auxiliary FilesDemonstration designs Xilinx Development System>> demo Perl scriptsAuxiliary Files perl <scriptname> -hXilinx System Generator v2.1 Reference Guide Xilinx Development System