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Xilinx V2.1 manual Common Options in Block Parameters Dialog Box, Xilinx LogiCORE Versions

Models: V2.1

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Xilinx Blockset Overview

Xilinx LogiCORE™ Versions

The Xilinx LogiCORE™ blocks (indicating the version numbers being supported by the System Generator) used in Xilinx System Generator v2.1 are listed below.

Xilinx Block	Xilinx LogiCORE		Version

Accumulator	ACCUMULATOR	V5.0
Addressable Shift	RAM_SHIFT	V5.0
Register
Adder/Subtractor	ADDSUB	V5.0
CIC	CIC	V1.0
Counter	BINARY_COUNTER	V5.0
Constant Multiplier	MULT_GEN	V4.0
Convolutional	CONVOLUTION	V1.0
Encoder
DDS	DDS	V4.0
Dual Port Ram	MEM_DP_BLOCK	V3.2
FIFO	SYNC_FIFO	V3.0
FFT	FFT and MEM_DP_BLOCK	V1.0	(Virtex, Spartan-II),
		V2.0	(Virtex-II)
		V3.2	(MEM_DP_BLOCK)
FIR Filter	DA_FIR	V6.0
Interleaver/	INTERLEAVER	V1.1
Deinterleaver
Inverter	GATE_BUS	V5.0
Logical	GATE_BUS	V5.0
Multiplier (mult)	MULT_GEN	V4.0
Mutiplexer (mux)	BUS_MUX	V5.0
Negate	TWOS_COMP	V5.0
Relational	COMPARE	V5.0
RS Decoder	RS_DECODER	V2.0
RS Encoder	RS_ENCODER	V2.0
Sine Cosine	SIN_COS	V3.0
Single Port RAM	MEM_SP_BLOCK and	V3.2(BRAM), V5.0 (dist.)
	DIST_MEM
State Machines	MEM_SP_BLOCK and	V3.2(BRAM), V5.0 (dist.)
	DIST_MEM
ROM	MEM_SP_BLOCK and	V3.2	(BRAM), V5.0 (dist.)
	DIST_MEM
Viterbi Decoder	VITERBI	V1.0

Common Options in Block Parameters Dialog Box

Each Xilinx block has several conﬁgurable parameters, seen in the block parameters dialog box. Many of these parameters are speciﬁc to that particular block. Those block

Common Options in Block Parameters Dialog Box

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Xilinx V2.1 manual Common Options in Block Parameters Dialog Box, Xilinx LogiCORE Versions, Xilinx Blockset Overview

Contents

Xilinx System Generator v2.1 for Printed in U.S.AXilinx Blocks System Generator Software Features Using the Xilinx Software Auxiliary FilesXilinx Development System Manual ContentsAbout This Manual Xilinx System Generator v2.1 Reference GuideResource Additional ResourcesDescription/URL Xilinx System Generator v2.1 Reference Guide ConventionsTypographical >> cd <your $MATLAB home directory>Chapter 2 Xilinx Blockset Overview ContentsChapter IntroductionXilinx Development System Xilinx System Generator v2.1 Reference GuideChapter 5 Using the Xilinx Software Chapter 4 System Generator Software FeaturesChapter 6 Auxiliary Files Xilinx Development System Chapter IntroductionIndustry and Product Overview Xilinx System Generator v2.1 Reference GuideSystem Generator System GeneratorSystem Level Modeling with System Generator IntroductionXilinx System Generator v2.1 Reference Guide The System Generator Design FlowXilinx Development System Simulink The System Generator Design FlowLibrary MATLAB EnvironmentXilinx System Generator v2.1 Reference Guide Arithmetic Data TypesXilinx Development System Introduction Hardware HandshakingMultirate Systems Hardware HandshakingXilinx Development System Bit-Trueand Cycle-TrueModelingAutomatic Testbench Generation Xilinx System Generator v2.1 Reference GuideXilinx Blockset Overview What is a Xilinx Block?What is a Xilinx Block? Chapter Xilinx Blockset OverviewXilinx Development System The Nature of Signals in the Xilinx BlocksetThe Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blockset Overview The Nature of Signals in the Xilinx BlocksetValid and Invalid Data Port Data TypesXilinx System Generator v2.1 Reference Guide Licensed CoresXilinx Development System Xilinx Blockset Overview Common Options in Block Parameters Dialog BoxXilinx LogiCORE Versions Common Options in Block Parameters Dialog BoxGenerate Core Use Placement Information for CoreArithmetic Type Implement with Xilinx Smart-IP Core if possibleOverride with Doubles PrecisionNumber of Bits Overﬂow and QuantizationXilinx Development System Sample PeriodUse Explicit Sample Period Xilinx System Generator v2.1 Reference GuideXilinx Blocks Chapter Xilinx BlocksBasic Elements System Generator∙System Clock Period Block Parameters Dialog Box∙Xilinx Product Family ∙Target Directory∙Generate button ∙Global Clock Enable and Global Clear∙Override with Doubles ∙Generate CoresXilinx Development System Addressable Shift RegisterBlock Interface Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx LogiCOREBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Black BoxIncorporating mixed language black boxes Block Parameters Dialog BoxFigure 3-3:Black Box block parameters dialog box Xilinx BlocksBasic Elements Xilinx System Generator v2.1 Reference Guide ConcatBlock Interface Block Parameters Dialog BoxXilinx Blocks ConstantConvert Block Parameters Dialog BoxFigure 3-7:Convert block parameters dialog box CounterBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx BlocksXilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-8:Counter block parameters dialog boxXilinx Blocks DelayXilinx LogiCORE Block Parameters Dialog BoxXilinx Development System Down SampleXilinx System Generator v2.1 Reference Guide Figure 3-11:Down sample circuit behaviorBasic Elements Get Valid BitBlock Parameters Dialog Box Xilinx BlocksFigure 3-13:Mux block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideBasic Elements Parallel to SerialBlock Interface Xilinx BlocksXilinx Development System RegisterBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-16:Register block parameters dialog box Block InterfaceBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide ReinterpretXilinx Development System Basic Elements Serial to ParallelBlock Parameters Dialog box Xilinx BlocksParameters speciﬁc to the block are Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Set Valid BitSlice Block Parameters Dialog BoxXilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-21:Slice block operationXilinx Blocks SyncBasic Elements Figure 3-23:Sync block use Xilinx System Generator v2.1 Reference GuideXilinx Development System Basic Elements Block Parameters Dialog BoxXilinx Blocks Figure 3-26:Sync block parameters dialog boxXilinx System Generator v2.1 Reference Guide Up SampleXilinx Development System Basic Elements Block Parameters Dialog BoxXilinx Blocks Figure 3-29:Up Sample block parameters dialog boxXilinx System Generator v2.1 Reference Guide CommunicationConvolutional Encoder Block InterfaceXilinx Blocks CommunicationBlock Parameters Dialog Box Xilinx LogiCOREXilinx Development System DepunctureXilinx System Generator v2.1 Reference Guide Figure 3-32:Example of Depuncture block useCommunication Interleaver DeinterleaverBlock Parameters Dialog Box Xilinx BlocksFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Block InterfaceBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide PunctureXilinx Development System Figure 3-38:Puncture block parameters dialog box RS DecoderBlock Parameters Dialog Box Xilinx BlocksXilinx Development System Block InterfaceXilinx System Generator v2.1 Reference Guide The port descriptions areXilinx Blocks Block Parameters Dialog BoxCommunication Xilinx System Generator v2.1 Reference Guide g x = ∏ x –ahxGS + i i =Xilinx Development System Xilinx Blocks RS EncoderLatency Xilinx LogiCoreXilinx System Generator v2.1 Reference Guide g x = x –ai x –ai + 1 . . . . x –ai + 2tc x = g x ⋅ i g x = x –a0 x –a1 x –a2 . . . . x –a15Xilinx Blocks Block InterfaceCommunication Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the RS Encoder block areXilinx Blocks g x = ∏ x –ahxGS + i i =Communication Xilinx System Generator v2.1 Reference Guide Viterbi DecoderLatency Xilinx LogiCoreBlock Parameters Dialog Box Block InterfaceCommunication Xilinx System Generator v2.1 Reference Guide Xilinx LogiCoreXilinx Development System Xilinx Blocks Block InterfaceFigure 3-46:Pipelined decimator and interpolator Figure 3-47:CIC block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-49:DDS block parameters dialog boxXilinx LogiCORE X k = ∑ xmW N mkXilinx Blocks Xilinx System Generator v2.1 Reference Guide W N = eBlock Interface Block Parameters Dialog BoxFigure 3-51 FFT Timing Diagram Block TimingXilinx Blocks Xilinx Development System Figure 3-52:FFT Timing CharacteristicsXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideBlock Interface yn = ∑ hixn –iXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-53:FIR block parameters dialog boxXilinx LogiCORE MathAccumulator MathParameters speciﬁc to the block are Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks AddSubBlock Parameters Dialog Box Xilinx LogiCOREFigure 3-56:CMult block parameters dialog box CMultBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideMath InverterXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide LogicalBlock Parameters Dialog Box Xilinx LogiCOREFigure 3-58:Logical block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx Development System MultBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Xilinx LogiCOREMath Xilinx LogiCORE NegateRelational Block Parameters Dialog BoxMath Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide ScaleShift Block Parameters Dialog BoxFigure 3-64:Shift block parameters dialog box SineCosineBlock Parameters Dialog Box Xilinx BlocksParameters speciﬁc to the SineCosine block are Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideMaximum Core ThresholdLatency Using Block Xilinx BlocksBlock Parameters Dialog Box Enabled SubsystemsMATLAB I/O Gateway BlocksXilinx Blocks Enable AdapterGateway In MATLAB I/OParameters speciﬁc to the Gateway In block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Gateway OutMATLAB I/O Parameters speciﬁc to the Gateway Out block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Display Quantization Error BlocksClear Quantization Error Quantization ErrorXilinx System Generator v2.1 Reference Guide MemoryDual Port RAM Block InterfaceXilinx Blocks MemoryFigure 3-70:Illustration of write modes Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areDepth log 2dXilinx LogiCORE Xilinx BlocksFigure 3-72:FIFO block parameters dialog box FIFOBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Xilinx LogiCOREMemory Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-73:ROM block parameters dialog boxDepth Xilinx LogiCORElog 2d Xilinx BlocksXilinx Development System Single Port RAMBlock Interface Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block Parameters Dialog BoxMemory Figure 3-75:Illustration of write modes Xilinx System Generator v2.1 Reference GuideXilinx Development System Memory Xilinx LogiCORElog 2d Xilinx BlocksXilinx Development System State MachineMealy State Machine Xilinx System Generator v2.1 Reference GuideXilinx Blocks State MachineXilinx System Generator v2.1 Reference Guide Moore State MachineBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks Figure 3-80:Moore State Machine block diagramState Machine Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-82:Construction of Next State and Output matricesState Machine Registered Mealy State MachineXilinx LogiCORE Xilinx BlocksXilinx Development System Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block Parameters Dialog BoxState Machine Xilinx System Generator v2.1 Reference Guide depth = 2k 2i = 2k +width = k + o N = depth × width = k + o2k + Xilinx LogiCOREXilinx Blocks Registered Moore State MachineState Machine Xilinx Development System Xilinx System Generator v2.1 Reference GuideXilinx Blocks ds = 2k 2i = 2k +N s = ds × ws = k 2k + Block Parameters Dialog BoxXilinx Development System Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide where>>setup Chapter System Generator Software FeaturesUsing the System Generator installer System Generator Software FeaturesXilinx System Generator v2.1 Reference Guide Using Black BoxesInstalled System Generator directory A Black Box ExampleFigure 4-1:Output of example black box function Using Black BoxesBlack Box window System Generator Software FeaturesXilinx Development System Use of mixed language projectsIncorporating mixed language black boxes Xilinx System Generator v2.1 Reference GuideSystem Generator Software Features Use of mixed language projectsFigure 4-2:Black Box block parameters dialog box Xilinx Development System Tips for creating a high performance designData Rate, Set ‘FAST’ Attribute Xilinx System Generator v2.1 Reference GuideMulticycle Path Constraints Using the System Generator Constraints FilesUsing the System Generator Constraints Files System Clock PeriodFigure 4-4:Example of a multirate design IOB Timing and Placement ConstraintsExample for showing constraints use Xilinx System Generator v2.1 Reference GuideUsing the System Generator Constraints Files System Generator Software FeaturesXilinx Development System Important IssuesConstraints Files Xilinx System Generator v2.1 Reference GuideFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features Xilinx System Generator v2.1 Reference Guide ∙sysgen.log - log ﬁleXilinx Development System Opening a System Generator project Chapter Using the Xilinx SoftwareUsing the Xilinx Software Xilinx ISE 4.1i Project NavigatorXilinx System Generator v2.1 Reference Guide Implementing your designXilinx Development System Xilinx ISE 4.1i Project Navigator Using the Xilinx SoftwareFigure 5-6:Properties of simulation process Xilinx System Generator v2.1 Reference GuideXilinx Development System Compiling your IP Using an EDIF software ﬂowUsing an EDIF software flow SimulationXilinx System Generator v2.1 Reference Guide MXE librariesXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Xilinx Development System Chapter Auxiliary FilesDemonstration designs Xilinx System Generator v2.1 Reference Guideperl <scriptname> -h Perl scriptsAuxiliary Files >> demoXilinx Development System Xilinx System Generator v2.1 Reference Guide