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Xilinx V2.1 manual Gateway Out, Xilinx Blocks, Matlab I/O

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Gateway Out

Xilinx Blocks

It should be noted there is a valid bit that accompanies the data signal. It is constrained at the same rate. For more information concerning the valid bit, refer to the Hardware Handshaking section in Chapter 1 of this manual.

If Data Rate, Set 'FAST' Attribute is selected, the OFFSET = IN constraints described above are produced. In addition, a FAST slew rate attribute is generated for each IOB. This reduces delay but increases noise and power consumption. For the previous example, the following additional attributes are added to the .ucf ﬁle

NET "Din<0>" FAST;

NET "Din<1>" FAST;

NET "Din<2>" FAST;

NET "Din_valid" FAST;

∙Specify IOB Location Constraints: Checking this option allows IOB location constraints to be speciﬁed.

∙IOB Pad Locations, e.g. {'Valid Bit', 'MSB', ...., 'LSB'}: IOB pin locations can be speciﬁed as a cell array of strings in this edit box. The locations are package-speciﬁc. For the above example, if a Virtex-E 2000 in a FG680 package is used, the location constraints for the Din bus can be speciﬁed in the dialog box as {'A36', 'C36', 'B36', 'D35'}. This is translated into constraints in the .ucf ﬁle in the following way:

# Loc constraints

NET "Din<0>" LOC = "D35";

NET "Din<1>" LOC = "B36";

NET "Din<2>" LOC = "C35";

NET "Din_valid" LOC = "A36";

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The Gateway In block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details.

Gateway Out

The Xilinx Gateway Out block is output from the Xilinx FPGA part of your Simulink design. It converts System Generator ﬁxed point data to Simulink double precision. According to its conﬁguration, it can either deﬁne an output port for the top level of the HDL design generated by System Generator, or be used simply as a test point that

will be trimmed from the hardware representation.

MATLAB I/O

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Xilinx V2.1 manual Gateway Out, Xilinx Blocks, Matlab I/O

Contents

Xilinx System Generator v2.1 for Printed in U.S.AXilinx Blocks System Generator Software Features Using the Xilinx Software Auxiliary FilesXilinx Development System Manual ContentsAbout This Manual Xilinx System Generator v2.1 Reference GuideAdditional Resources ResourceDescription/URL Xilinx System Generator v2.1 Reference Guide ConventionsTypographical >> cd <your $MATLAB home directory>Chapter 2 Xilinx Blockset Overview ContentsChapter IntroductionXilinx Development System Xilinx System Generator v2.1 Reference GuideChapter 4 System Generator Software Features Chapter 5 Using the Xilinx SoftwareChapter 6 Auxiliary Files Xilinx Development System Chapter IntroductionIndustry and Product Overview Xilinx System Generator v2.1 Reference GuideSystem Generator System GeneratorSystem Level Modeling with System Generator IntroductionThe System Generator Design Flow Xilinx System Generator v2.1 Reference GuideXilinx Development System Simulink The System Generator Design FlowLibrary MATLAB EnvironmentArithmetic Data Types Xilinx System Generator v2.1 Reference GuideXilinx Development System Introduction Hardware HandshakingMultirate Systems Hardware HandshakingXilinx Development System Bit-Trueand Cycle-TrueModelingAutomatic Testbench Generation Xilinx System Generator v2.1 Reference GuideXilinx Blockset Overview What is a Xilinx Block?What is a Xilinx Block? Chapter Xilinx Blockset OverviewXilinx Development System The Nature of Signals in the Xilinx BlocksetThe Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blockset Overview The Nature of Signals in the Xilinx BlocksetValid and Invalid Data Port Data TypesLicensed Cores Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blockset Overview Common Options in Block Parameters Dialog BoxXilinx LogiCORE Versions Common Options in Block Parameters Dialog BoxGenerate Core Use Placement Information for CoreArithmetic Type Implement with Xilinx Smart-IP Core if possibleOverride with Doubles PrecisionNumber of Bits Overﬂow and QuantizationXilinx Development System Sample PeriodUse Explicit Sample Period Xilinx System Generator v2.1 Reference GuideXilinx Blocks Chapter Xilinx BlocksBasic Elements System Generator∙System Clock Period Block Parameters Dialog Box∙Xilinx Product Family ∙Target Directory∙Generate button ∙Global Clock Enable and Global Clear∙Override with Doubles ∙Generate CoresXilinx Development System Addressable Shift RegisterBlock Interface Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx LogiCOREBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Black BoxIncorporating mixed language black boxes Block Parameters Dialog BoxXilinx Blocks Figure 3-3:Black Box block parameters dialog boxBasic Elements Xilinx System Generator v2.1 Reference Guide ConcatBlock Interface Block Parameters Dialog BoxXilinx Blocks ConstantConvert Block Parameters Dialog BoxFigure 3-7:Convert block parameters dialog box CounterBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx BlocksXilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-8:Counter block parameters dialog boxXilinx Blocks DelayXilinx LogiCORE Block Parameters Dialog BoxXilinx Development System Down SampleXilinx System Generator v2.1 Reference Guide Figure 3-11:Down sample circuit behaviorBasic Elements Get Valid BitBlock Parameters Dialog Box Xilinx BlocksFigure 3-13:Mux block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideBasic Elements Parallel to SerialBlock Interface Xilinx BlocksXilinx Development System RegisterBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-16:Register block parameters dialog box Block InterfaceBlock Parameters Dialog Box Xilinx BlocksReinterpret Xilinx System Generator v2.1 Reference GuideXilinx Development System Basic Elements Serial to ParallelBlock Parameters Dialog box Xilinx BlocksParameters speciﬁc to the block are Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Set Valid BitSlice Block Parameters Dialog BoxXilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-21:Slice block operationSync Xilinx BlocksBasic Elements Xilinx System Generator v2.1 Reference Guide Figure 3-23:Sync block useXilinx Development System Basic Elements Block Parameters Dialog BoxXilinx Blocks Figure 3-26:Sync block parameters dialog boxUp Sample Xilinx System Generator v2.1 Reference GuideXilinx Development System Basic Elements Block Parameters Dialog BoxXilinx Blocks Figure 3-29:Up Sample block parameters dialog boxXilinx System Generator v2.1 Reference Guide CommunicationConvolutional Encoder Block InterfaceXilinx Blocks CommunicationBlock Parameters Dialog Box Xilinx LogiCOREXilinx Development System DepunctureXilinx System Generator v2.1 Reference Guide Figure 3-32:Example of Depuncture block useCommunication Interleaver DeinterleaverBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Figure 3-34:Forney convolutional interleaver with a constant difference between consecutive branchesXilinx Development System Xilinx Blocks Block InterfaceBlock Parameters Dialog Box Xilinx LogiCOREPuncture Xilinx System Generator v2.1 Reference GuideXilinx Development System Figure 3-38:Puncture block parameters dialog box RS DecoderBlock Parameters Dialog Box Xilinx BlocksXilinx Development System Block InterfaceXilinx System Generator v2.1 Reference Guide The port descriptions areBlock Parameters Dialog Box Xilinx BlocksCommunication g x = ∏ x –ahxGS + i i = Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks RS EncoderLatency Xilinx LogiCoreXilinx System Generator v2.1 Reference Guide g x = x –ai x –ai + 1 . . . . x –ai + 2tc x = g x ⋅ i g x = x –a0 x –a1 x –a2 . . . . x –a15Block Interface Xilinx BlocksCommunication Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the RS Encoder block areg x = ∏ x –ahxGS + i i = Xilinx BlocksCommunication Xilinx System Generator v2.1 Reference Guide Viterbi DecoderLatency Xilinx LogiCoreBlock Interface Block Parameters Dialog BoxCommunication Xilinx LogiCore Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Interface Xilinx BlocksFigure 3-46:Pipelined decimator and interpolator Figure 3-47:CIC block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-49:DDS block parameters dialog boxX k = ∑ xmW N mk Xilinx LogiCOREXilinx Blocks Xilinx System Generator v2.1 Reference Guide W N = eBlock Interface Block Parameters Dialog BoxBlock Timing Figure 3-51 FFT Timing DiagramXilinx Blocks Xilinx Development System Figure 3-52:FFT Timing CharacteristicsXilinx LogiCORE Xilinx System Generator v2.1 Reference Guideyn = ∑ hixn –i Block InterfaceXilinx Blocks Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-53:FIR block parameters dialog boxXilinx LogiCORE MathAccumulator MathParameters speciﬁc to the block are Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks AddSubBlock Parameters Dialog Box Xilinx LogiCOREFigure 3-56:CMult block parameters dialog box CMultBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideMath InverterXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide LogicalBlock Parameters Dialog Box Xilinx LogiCOREFigure 3-58:Logical block parameters dialog box Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx Development System MultBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE Xilinx BlocksMath Xilinx LogiCORE NegateRelational Block Parameters Dialog BoxMath Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide ScaleShift Block Parameters Dialog BoxFigure 3-64:Shift block parameters dialog box SineCosineBlock Parameters Dialog Box Xilinx BlocksParameters speciﬁc to the SineCosine block are Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideMaximum Core ThresholdLatency Using Block Xilinx BlocksBlock Parameters Dialog Box Enabled SubsystemsMATLAB I/O Gateway BlocksXilinx Blocks Enable AdapterGateway In MATLAB I/OXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway In block areXilinx Development System Gateway Out Xilinx BlocksMATLAB I/O Xilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the Gateway Out block areXilinx Development System Display Quantization Error BlocksClear Quantization Error Quantization ErrorXilinx System Generator v2.1 Reference Guide MemoryDual Port RAM Block InterfaceMemory Xilinx BlocksFigure 3-70:Illustration of write modes Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areDepth log 2dXilinx LogiCORE Xilinx BlocksFigure 3-72:FIFO block parameters dialog box FIFOBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE Xilinx BlocksMemory Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-73:ROM block parameters dialog boxDepth Xilinx LogiCORElog 2d Xilinx BlocksXilinx Development System Single Port RAMBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Xilinx BlocksMemory Xilinx System Generator v2.1 Reference Guide Figure 3-75:Illustration of write modesXilinx Development System Memory Xilinx LogiCORElog 2d Xilinx BlocksXilinx Development System State MachineMealy State Machine Xilinx System Generator v2.1 Reference GuideXilinx Blocks State MachineXilinx System Generator v2.1 Reference Guide Moore State MachineBlock Parameters Dialog Box Xilinx LogiCOREFigure 3-80:Moore State Machine block diagram Xilinx BlocksState Machine Xilinx Development System Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-82:Construction of Next State and Output matricesState Machine Registered Mealy State MachineXilinx LogiCORE Xilinx BlocksXilinx Development System Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Xilinx BlocksState Machine Xilinx System Generator v2.1 Reference Guide depth = 2k 2i = 2k +width = k + o N = depth × width = k + o2k + Xilinx LogiCORERegistered Moore State Machine Xilinx BlocksState Machine Xilinx Development System Xilinx System Generator v2.1 Reference GuideXilinx Blocks ds = 2k 2i = 2k +N s = ds × ws = k 2k + Block Parameters Dialog BoxXilinx Development System Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide where>>setup Chapter System Generator Software FeaturesUsing the System Generator installer System Generator Software FeaturesXilinx System Generator v2.1 Reference Guide Using Black BoxesInstalled System Generator directory A Black Box ExampleFigure 4-1:Output of example black box function Using Black BoxesBlack Box window System Generator Software FeaturesXilinx Development System Use of mixed language projectsIncorporating mixed language black boxes Xilinx System Generator v2.1 Reference GuideUse of mixed language projects System Generator Software FeaturesFigure 4-2:Black Box block parameters dialog box Xilinx Development System Tips for creating a high performance designData Rate, Set ‘FAST’ Attribute Xilinx System Generator v2.1 Reference GuideMulticycle Path Constraints Using the System Generator Constraints FilesUsing the System Generator Constraints Files System Clock PeriodFigure 4-4:Example of a multirate design IOB Timing and Placement ConstraintsExample for showing constraints use Xilinx System Generator v2.1 Reference GuideUsing the System Generator Constraints Files System Generator Software FeaturesXilinx Development System Important IssuesConstraints Files Xilinx System Generator v2.1 Reference GuideFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features ∙sysgen.log - log ﬁle Xilinx System Generator v2.1 Reference GuideXilinx Development System Opening a System Generator project Chapter Using the Xilinx SoftwareUsing the Xilinx Software Xilinx ISE 4.1i Project NavigatorImplementing your design Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx ISE 4.1i Project Navigator Using the Xilinx SoftwareXilinx System Generator v2.1 Reference Guide Figure 5-6:Properties of simulation processXilinx Development System Compiling your IP Using an EDIF software ﬂowUsing an EDIF software flow SimulationMXE libraries Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Xilinx Development System Chapter Auxiliary FilesDemonstration designs Xilinx System Generator v2.1 Reference Guideperl <scriptname> -h Perl scriptsAuxiliary Files >> demoXilinx Development System Xilinx System Generator v2.1 Reference Guide