Xilinx V2.1 manual Using the Xilinx Software, Xilinx ISE 4.1i Project Navigator

Using the Xilinx Software

In the Sources window, select the top-level VHDL module in your design. Now you will notice that the Process window shows you all available processes that can be run on the top-level VHDL module.

Figure 5-3: Processes available to VHDL design source

In the Process window, if you right-click on Generate Programming File and select Run, you are instructing Project Navigator to run through whatever processes are necessary to produce a programming file (FPGA bitstream) from the selected VHDL source. In the messages console window, you will see that Project Navigator is synthesizing, translating, mapping, routing, and generating a bitstream for your design.

Now that you have generated a bitstream for your design, you have access to all the files that were produced on the way to bitstream creation. For example, if you wish to see how your design was placed on the Xilinx FPGA, you can select the FloorPlanner view underneath the Place & Route option in the Process window.

Figure 5-4: Launching processes from within Project Navigator

Simulating using ModelSim within the Project Navigator

The System Generator project is already set up to run simulations at four different stages of Project Navigator implementation. The System Generator creates four different ModelSim do files which can be run from the Simulation process when your testbench is selected.

The ModelSim do files created by System Generator are:

∙pn_behavioral.do - for a behavioral (VHDL) simulation on the VHDL files in the project, before any synthesis or implementation.

Xilinx ISE 4.1i Project Navigator 141