Xilinx V2.1 manual Use of mixed language projects, Incorporating mixed language black boxes

Xilinx System Generator v2.1 Reference Guide

Use of mixed language projects

System Generator v2.1 supports mixed language (VHDL and Verilog HDL) projects, as explained below.

The System Generator’s code-generation software creates VHDL code from the system representation (Xilinx Blockset portion) of your design. Even though VHDL is the only choice for the generated output language, System Generator supports mixed language designs in two ways:

∙You can incorporate Verilog into a System Generator design as a black box.

∙You can also incorporate the VHDL created by System Generator into a larger Verilog system.

In order to mix VHDL and Verilog, you must have a mixed language simulator and a mixed language synthesis compiler. Tools that support mixed language projects usually have special restrictions and instructions for their mixed language interfaces, e.g.,

∙instructions for the instantiation location of a Verilog design unit within the

VHDL

∙instructions for the instantiation location of a VHDL design unit within the Verilog

Designs that mix VHDL with Verilog can have problems if parameters or generics are passed across the language boundaries. System Generator avoids these problems by ensuring that this situation does not arise.

Incorporating mixed language black boxes

A Verilog black box is configured in almost the same way as a VHDL black box. As with VHDL, the instructions are entered in the Black Box block parameters dialog box that is associated to the black box token. Under HDL Language, select Verilog, then

130 Xilinx Development System