Xilinx V2.1 manual Set Valid Bit, Slice

Xilinx Blocks

∙Binary Point: Output binary point location

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Parallel to Serial block does not use a Xilinx LogiCORE.

An error is reported when the number of output bits cannot be divided evenly by the number of input bits. The minimum latency for this block is zero.

Set Valid Bit

The Xilinx Set Valid Bit block flags input data as invalid when the signal on the valid bit input port is zero. This block only sets data invalid; it cannot change input data to valid.

In the Xilinx Blockset, every data sample that flows through the model is accompanied by a handshake validation signal. In the corresponding hardware, every data-carrying bus has a companion net that carries a valid or invalid

status indicator. This block provides some explicit control over this handshake mechanism.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-20: Set Valid Bit block parameters dialog box

Slice

The Xilinx Slice block allows you to slice off a sequence of bits from your input data and create a new data value. This value is presented as the output from the block. The output data type is unsigned with its binary point at zero.

The block provides several mechanisms by which the sequence of bits can be specified. If the input type is known at the time of parameterization, the various mechanisms do not offer any gain in functionality. If, however, a Slice block is used in a design where the input data width or binary point position are subject to change, the variety of mechanisms becomes useful. The block can be configured, for example, always to extract only the top bit of the input, or only the integral bits, or

Basic Elements 45