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Xilinx V2.1 manual Gateway In, Enable Adapter, Matlab I/O, Xilinx Blocks

Models: V2.1

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Enable Adapter

Xilinx Blocks

LogiCOREs, as well as signals and control circuits to drive the clock network. Consequently, most System Generator blocks do not provide an explicit enable port. There are two exceptions> the Register block and the Addressable Shift Register block, which fundamentally require a CE port in order to target a high performance hardware implementation.

Simulink Enabled Subsystems can be used to enable blocks and subsystems. In order to support System Generator’s bit and cycle true modeling in Simulink, it is required that the enable port on an enabled subsystem be driven by the Enable Adapter block, found in the Xilinx blockset’s MATLAB I/O library. An example of this requirement is shown in the ﬁgure below. This shows an address generation model for a MAC-based FIR ﬁlter. The DownCount subsystem is stalled for a single sample period when the CoefCount counter value is equal to the number of ﬁlter taps (in this case, 96 taps).

Figure 3-67: Example of enabled subsystem

The following blocks cannot be placed in an enabled subsystem with System Generator v2.1. The blocks are: CIC, Convolutional Encoder, FIR, FFT, Gateway In, Gateway Out, RS Decoder, RS Encoder, and Viterbi Decoder.

Enable Adapter

When using an enabled subsystem that contains Xilinx blocks, the enable port must be driven by a Xilinx Enable Adapter block. This block is a required interface to any enabled subsystem that contains a System Generator block. The Enable Adapter block’s output port must drive the subsystem’s enable port.

Gateway In

The Xilinx Gateway In block is the input into the Xilinx FPGA part of your Simulink design. It converts Simulink double precision input to the System Generator ﬁxed point type, and deﬁnes an input port for the top level of the HDL design generated by System Generator.

MATLAB I/O

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Xilinx V2.1 manual Gateway In, Enable Adapter, Matlab I/O, Xilinx Blocks

Contents

Xilinx Blocks System Generator Software Features Printed in U.S.AUsing the Xilinx Software Auxiliary Files Xilinx System Generator v2.1 forAbout This Manual Manual ContentsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemResource Additional ResourcesDescription/URL Typographical Conventions>> cd <your $MATLAB home directory> Xilinx System Generator v2.1 Reference GuideChapter ContentsIntroduction Chapter 2 Xilinx Blockset OverviewXilinx Development System Xilinx System Generator v2.1 Reference GuideChapter 5 Using the Xilinx Software Chapter 4 System Generator Software FeaturesChapter 6 Auxiliary Files Industry and Product Overview Chapter IntroductionXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Level Modeling with System Generator System GeneratorIntroduction System GeneratorXilinx System Generator v2.1 Reference Guide The System Generator Design FlowXilinx Development System Library The System Generator Design FlowMATLAB Environment SimulinkXilinx System Generator v2.1 Reference Guide Arithmetic Data TypesXilinx Development System Multirate Systems Hardware HandshakingHardware Handshaking IntroductionAutomatic Testbench Generation Bit-Trueand Cycle-TrueModelingXilinx System Generator v2.1 Reference Guide Xilinx Development SystemWhat is a Xilinx Block? What is a Xilinx Block?Chapter Xilinx Blockset Overview Xilinx Blockset OverviewThe Block Parameters Dialog Box The Nature of Signals in the Xilinx BlocksetXilinx System Generator v2.1 Reference Guide Xilinx Development SystemValid and Invalid Data The Nature of Signals in the Xilinx BlocksetPort Data Types Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Licensed CoresXilinx Development System Xilinx LogiCORE Versions Common Options in Block Parameters Dialog BoxCommon Options in Block Parameters Dialog Box Xilinx Blockset OverviewArithmetic Type Use Placement Information for CoreImplement with Xilinx Smart-IP Core if possible Generate CoreNumber of Bits PrecisionOverﬂow and Quantization Override with DoublesUse Explicit Sample Period Sample PeriodXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBasic Elements Chapter Xilinx BlocksSystem Generator Xilinx Blocks∙Xilinx Product Family Block Parameters Dialog Box∙Target Directory ∙System Clock Period∙Override with Doubles ∙Global Clock Enable and Global Clear∙Generate Cores ∙Generate buttonBlock Interface Addressable Shift RegisterXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks Basic ElementsIncorporating mixed language black boxes Black BoxBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-3:Black Box block parameters dialog box Xilinx BlocksBasic Elements Block Interface ConcatBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideConvert ConstantBlock Parameters Dialog Box Xilinx BlocksBlock Parameters Dialog Box CounterXilinx System Generator v2.1 Reference Guide Figure 3-7:Convert block parameters dialog boxBasic Elements Xilinx BlocksXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-8:Counter block parameters dialog box Xilinx Development SystemXilinx LogiCORE DelayBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Down SampleFigure 3-11:Down sample circuit behavior Xilinx Development SystemBlock Parameters Dialog Box Get Valid BitXilinx Blocks Basic ElementsXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-13:Mux block parameters dialog boxBlock Interface Parallel to SerialXilinx Blocks Basic ElementsBlock Parameters Dialog Box RegisterXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Block InterfaceXilinx Blocks Figure 3-16:Register block parameters dialog boxXilinx System Generator v2.1 Reference Guide ReinterpretXilinx Development System Block Parameters Dialog box Serial to ParallelXilinx Blocks Basic ElementsBlock Parameters Dialog Box Block InterfaceXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areSlice Set Valid BitBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-21:Slice block operation Xilinx Development SystemXilinx Blocks SyncBasic Elements Figure 3-23:Sync block use Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Block Parameters Dialog BoxFigure 3-26:Sync block parameters dialog box Basic ElementsXilinx System Generator v2.1 Reference Guide Up SampleXilinx Development System Xilinx Blocks Block Parameters Dialog BoxFigure 3-29:Up Sample block parameters dialog box Basic ElementsConvolutional Encoder CommunicationBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box CommunicationXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide DepunctureFigure 3-32:Example of Depuncture block use Xilinx Development SystemBlock Parameters Dialog Box Interleaver DeinterleaverXilinx Blocks CommunicationFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Xilinx System Generator v2.1 Reference GuideXilinx Development System Block Parameters Dialog Box Block InterfaceXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide PunctureXilinx Development System Block Parameters Dialog Box RS DecoderXilinx Blocks Figure 3-38:Puncture block parameters dialog boxXilinx System Generator v2.1 Reference Guide Block InterfaceThe port descriptions are Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxCommunication Xilinx System Generator v2.1 Reference Guide g x = ∏ x –ahxGS + i i =Xilinx Development System Latency RS EncoderXilinx LogiCore Xilinx Blocksc x = g x ⋅ i g x = x –ai x –ai + 1 . . . . x –ai + 2tg x = x –a0 x –a1 x –a2 . . . . x –a15 Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block InterfaceCommunication Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxParameters speciﬁc to the RS Encoder block are Xilinx Development SystemXilinx Blocks g x = ∏ x –ahxGS + i i =Communication Latency Viterbi DecoderXilinx LogiCore Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Block InterfaceCommunication Xilinx System Generator v2.1 Reference Guide Xilinx LogiCoreXilinx Development System Xilinx Blocks Block InterfaceFigure 3-46:Pipelined decimator and interpolator Xilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-47:CIC block parameters dialog boxXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-49:DDS block parameters dialog box Xilinx Development SystemXilinx LogiCORE X k = ∑ xmW N mkXilinx Blocks Block Interface W N = eBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-51 FFT Timing Diagram Block TimingXilinx Blocks Xilinx LogiCORE Figure 3-52:FFT Timing CharacteristicsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Interface yn = ∑ hixn –iXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-53:FIR block parameters dialog box Xilinx Development SystemAccumulator MathMath Xilinx LogiCOREXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areBlock Parameters Dialog Box AddSubXilinx LogiCORE Xilinx BlocksBlock Parameters Dialog Box CMultXilinx System Generator v2.1 Reference Guide Figure 3-56:CMult block parameters dialog boxXilinx LogiCORE InverterXilinx Blocks MathBlock Parameters Dialog Box LogicalXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks Figure 3-58:Logical block parameters dialog boxBlock Parameters Dialog Box MultXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Xilinx LogiCOREMath Relational NegateBlock Parameters Dialog Box Xilinx LogiCOREXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks MathShift ScaleBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box SineCosineXilinx Blocks Figure 3-64:Shift block parameters dialog boxXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the SineCosine block areLatency Using Block ThresholdXilinx Blocks Maximum CoreMATLAB I/O Enabled SubsystemsGateway Blocks Block Parameters Dialog BoxGateway In Enable AdapterMATLAB I/O Xilinx BlocksParameters speciﬁc to the Gateway In block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Gateway OutMATLAB I/O Parameters speciﬁc to the Gateway Out block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Clear Quantization Error Quantization Error BlocksQuantization Error DisplayDual Port RAM MemoryBlock Interface Xilinx System Generator v2.1 Reference GuideXilinx Blocks MemoryFigure 3-70:Illustration of write modes Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxParameters speciﬁc to the block are Xilinx Development SystemXilinx LogiCORE log 2dXilinx Blocks DepthBlock Parameters Dialog Box FIFOXilinx System Generator v2.1 Reference Guide Figure 3-72:FIFO block parameters dialog boxXilinx Blocks Xilinx LogiCOREMemory Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-73:ROM block parameters dialog box Xilinx Development Systemlog 2d Xilinx LogiCOREXilinx Blocks DepthBlock Interface Single Port RAMXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxMemory Figure 3-75:Illustration of write modes Xilinx System Generator v2.1 Reference GuideXilinx Development System log 2d Xilinx LogiCOREXilinx Blocks MemoryMealy State Machine State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks State MachineBlock Parameters Dialog Box Moore State MachineXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks Figure 3-80:Moore State Machine block diagramState Machine Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-82:Construction of Next State and Output matrices Xilinx Development SystemXilinx LogiCORE Registered Mealy State MachineXilinx Blocks State MachineXilinx Development System Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block Parameters Dialog BoxState Machine width = k + o N = depth × width = k + o2k + depth = 2k 2i = 2k +Xilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx Blocks Registered Moore State MachineState Machine Xilinx Development System Xilinx System Generator v2.1 Reference GuideN s = ds × ws = k 2k + ds = 2k 2i = 2k +Block Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Xilinx LogiCOREwhere Xilinx Development SystemUsing the System Generator installer Chapter System Generator Software FeaturesSystem Generator Software Features >>setupInstalled System Generator directory Using Black BoxesA Black Box Example Xilinx System Generator v2.1 Reference GuideBlack Box window Using Black BoxesSystem Generator Software Features Figure 4-1:Output of example black box functionIncorporating mixed language black boxes Use of mixed language projectsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Use of mixed language projectsFigure 4-2:Black Box block parameters dialog box Data Rate, Set ‘FAST’ Attribute Tips for creating a high performance designXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUsing the System Generator Constraints Files Using the System Generator Constraints FilesSystem Clock Period Multicycle Path ConstraintsExample for showing constraints use IOB Timing and Placement ConstraintsXilinx System Generator v2.1 Reference Guide Figure 4-4:Example of a multirate designUsing the System Generator Constraints Files System Generator Software FeaturesConstraints Files Important IssuesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features Xilinx System Generator v2.1 Reference Guide ∙sysgen.log - log ﬁleXilinx Development System Using the Xilinx Software Chapter Using the Xilinx SoftwareXilinx ISE 4.1i Project Navigator Opening a System Generator projectXilinx System Generator v2.1 Reference Guide Implementing your designXilinx Development System Xilinx ISE 4.1i Project Navigator Using the Xilinx SoftwareFigure 5-6:Properties of simulation process Xilinx System Generator v2.1 Reference GuideXilinx Development System Using an EDIF software flow Using an EDIF software ﬂowSimulation Compiling your IPXilinx System Generator v2.1 Reference Guide MXE librariesXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Demonstration designs Chapter Auxiliary FilesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemAuxiliary Files Perl scripts>> demo perl <scriptname> -hXilinx Development System Xilinx System Generator v2.1 Reference Guide