Xilinx System Generator v2.1 Reference Guide

cell array of strings in the box labeled IOB Pad Locations. Locations are package- specific; in this example a Virtex-E 2000 in a FG680 package is used. The location constraints for the Din bus are provided in the dialog box as {'A36', 'C36', 'B36', 'D35'}. This is translated into constraints in the .ucf file in the following way:

# Loc constraints

NET "Din<0>" LOC = "D35";

NET "Din<1>" LOC = "B36";

NET "Din<2>" LOC = "C35";

NET "Din_valid" LOC = "A36";

Important Issues

(1)It is important to note that design hierarchy is used to specify the assignment of blocks to clock groups. The project files created by System Generator for XST (Xilinx Synthesis Technology), Synplify and Leonardo Spectrum tell the synthesis tools to preserve this hierarchy. If hierarchy is not preserved, block names will change and constraints will no longer work.

(2)XST downcases instance and port names. If the names of blocks in your Simulink model contain capital letters, you will get warning messages like the following from the Xilinx downstream software translate step, ngdbuild:

WARNING:NgdBuild:383 - A case sensitive search for the INST, PAD, or NET element refered to by a constraint entry in the UCF file that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but warnings will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user- specified identifiers, which includes names of logic elements in a design. For the sake of compatibility with currently existing .xnf, .xtf, and .xff files, Software will allow a case insensitive search for INST, PAD, or NET elements referenced in a .ucf file.

WARNING:NgdBuild:384 - Found case insensitive match for INST name 'Delay1'. INST is 'delay1'.

Constraints Files

System Generator writes constraints to two files. The files are identical except for the notation used to identify buses. If the design is named my_project, the files are my_project.ucf and my_project_paren.ucf.

In my_project.ucf, buses are denoted with angle brackets. This file should be used with XST from within Xilinx ISE 4.1i Project Navigator and with Synplify and Leonardo Spectrum when using the project files created by System Generator.

In my_project_paren.ucf, buses are denoted with parentheses. This file is needed only when using Synplify or Leonardo Spectrum from within Project Navigator. When this is the case, you should discard the original my_project.ucf, and rename my_project_paren.ucf to my_project.ucf.

136

Xilinx Development System

Page 135 Page 137
Page 136
Image 136
Xilinx V2.1 manual Important Issues, Constraints Files
Page 135 Page 137

V2.1 specifications

Xilinx V2.1 is a notable iteration in the series of versatile and robust Field-Programmable Gate Arrays (FPGAs) developed to cater to a wide range of applications. Launched to provide enhancements in performance and flexibility, V2.1 embodies sophisticated technologies and features that stand out in the electronics industry.

One of the primary features of Xilinx V2.1 is its improved processing power. The architecture has been optimized to support higher clock speeds and increased logic density, allowing for more complex designs to be implemented effectively. This boost in performance is facilitated by utilizing advanced silicon technologies, which significantly reduce power consumption while maximizing efficiency.

Another significant characteristic of Xilinx V2.1 is its enhanced I/O (Input/Output) capabilities. The device supports a variety of industry-standard interfaces, which include PCI Express, SATA, and various serial communication protocols. Such adaptability ensures seamless integration into existing systems, providing engineers with the flexibility to adapt to various application requirements without the need for substantial redesign efforts.

Xilinx V2.1 also features improved scalability, making it a prime choice for applications that demand diverse performance levels. This device supports an array of configurations and can be used in small-scale projects as well as in larger, more demanding environments requiring extensive resources. This scalability is further aided by support for multiple development platforms, enabling rapid prototyping and simplifying the design process.

Security is increasingly becoming a priority in digital design, and Xilinx V2.1 addresses this concern via hardware security features. It includes enhanced encryption protocols and secure boot functionalities, which help protect intellectual property and sensitive data from unauthorized access.

Additionally, the integration of advanced DSP (Digital Signal Processing) blocks allows Xilinx V2.1 to efficiently handle data-intensive tasks such as video processing and real-time signal analysis. These capabilities make it suitable for applications in telecommunications, automotive systems, and industrial automation.

Xilinx V2.1 also benefits from a rich development environment, including robust software tools that facilitate design entry, simulation, and verification. The support for industry-standard programming languages like VHDL and Verilog simplifies the development process, enabling engineers to design complex systems more efficiently.

In summary, Xilinx V2.1 stands out due to its impressive combination of high performance, flexibility, scalability, security, and comprehensive development support. These features make it a valuable asset for engineers and developers looking to innovate across various sectors, from telecommunications and automotive to industrial applications.
Top Page Image Contents