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Xilinx V2.1 manual Block Interface, Xilinx Blocks, Communication

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Xilinx Blocks

Block Interface

The Xilinx RS Encoder block has two inputs (din, rst) and three output (dout, info and rfd) ports. The RS Encoder block also has optional start and bypass input ports.

Figure 3-43: Reed-Solomon Encoder icons, including optional ports

The port descriptions are:

∙din: carries the input information symbols of the RS code. The din signal must be an UFixS_0 where S is equal to the symbol width (3 to 12).

∙rst: carries the reset signal for the RS encoder. After the rst signal is asserted the RS encoder initializes the next available input as the ﬁrst information symbol. The rst signal must be a UFix1_0.

∙start: when start is asserted for a particular sample period, the data on the din port is taken as the ﬁrst input information symbol. If start is asserted high for more than one sample period, the data at the last sample period is taken as the ﬁrst input information symbol. The start signal is ignored if bypass is asserted high for the same sample period. The start signal always resets the state of the code generator. The start signal must be a UFix1_0.

∙bypass: when bypass is asserted for a particular sample period, the corresponding data input on the din port is passed straight through to the dout port with a 4 (6 in case of CCSDS) sample period delay. The bypass signal has no effect on the state of the code generator. The bypass signal must be a UFix1_0.

∙dout: carries the input information symbols and the parity symbols of the RS code. The dout signal has the same arithmetic type as the din input.

∙info: The info output is 1 when there is information symbols on the dout port. The info output is also 1 when the bypass asserted input data appears at the dout port. The info signal is a UFix1_0.

∙rfd: carries the ready for data signal for the RS encoder. This signal is 1 till the RS encoder is accepting information symbols and 0 when the RS encoder is outputting parity symbols. The rfd signal is a UFix1_0.

Communication

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Xilinx V2.1 manual Block Interface, Xilinx Blocks, Communication

Contents

Xilinx Blocks System Generator Software Features Printed in U.S.AUsing the Xilinx Software Auxiliary Files Xilinx System Generator v2.1 forAbout This Manual Manual ContentsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemDescription/URL Additional ResourcesResource Typographical Conventions>> cd <your $MATLAB home directory> Xilinx System Generator v2.1 Reference GuideChapter ContentsIntroduction Chapter 2 Xilinx Blockset OverviewXilinx Development System Xilinx System Generator v2.1 Reference GuideChapter 6 Auxiliary Files Chapter 4 System Generator Software FeaturesChapter 5 Using the Xilinx Software Industry and Product Overview Chapter IntroductionXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Level Modeling with System Generator System GeneratorIntroduction System GeneratorXilinx Development System The System Generator Design FlowXilinx System Generator v2.1 Reference Guide Library The System Generator Design FlowMATLAB Environment SimulinkXilinx Development System Arithmetic Data TypesXilinx System Generator v2.1 Reference Guide Multirate Systems Hardware HandshakingHardware Handshaking IntroductionAutomatic Testbench Generation Bit-Trueand Cycle-TrueModelingXilinx System Generator v2.1 Reference Guide Xilinx Development SystemWhat is a Xilinx Block? What is a Xilinx Block?Chapter Xilinx Blockset Overview Xilinx Blockset OverviewThe Block Parameters Dialog Box The Nature of Signals in the Xilinx BlocksetXilinx System Generator v2.1 Reference Guide Xilinx Development SystemValid and Invalid Data The Nature of Signals in the Xilinx BlocksetPort Data Types Xilinx Blockset OverviewXilinx Development System Licensed CoresXilinx System Generator v2.1 Reference Guide Xilinx LogiCORE Versions Common Options in Block Parameters Dialog BoxCommon Options in Block Parameters Dialog Box Xilinx Blockset OverviewArithmetic Type Use Placement Information for CoreImplement with Xilinx Smart-IP Core if possible Generate CoreNumber of Bits PrecisionOverﬂow and Quantization Override with DoublesUse Explicit Sample Period Sample PeriodXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBasic Elements Chapter Xilinx BlocksSystem Generator Xilinx Blocks∙Xilinx Product Family Block Parameters Dialog Box∙Target Directory ∙System Clock Period∙Override with Doubles ∙Global Clock Enable and Global Clear∙Generate Cores ∙Generate buttonBlock Interface Addressable Shift RegisterXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks Basic ElementsIncorporating mixed language black boxes Black BoxBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx BlocksFigure 3-3:Black Box block parameters dialog box Block Interface ConcatBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideConvert ConstantBlock Parameters Dialog Box Xilinx BlocksBlock Parameters Dialog Box CounterXilinx System Generator v2.1 Reference Guide Figure 3-7:Convert block parameters dialog boxBasic Elements Xilinx BlocksXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-8:Counter block parameters dialog box Xilinx Development SystemXilinx LogiCORE DelayBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Down SampleFigure 3-11:Down sample circuit behavior Xilinx Development SystemBlock Parameters Dialog Box Get Valid BitXilinx Blocks Basic ElementsXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-13:Mux block parameters dialog boxBlock Interface Parallel to SerialXilinx Blocks Basic ElementsBlock Parameters Dialog Box RegisterXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box Block InterfaceXilinx Blocks Figure 3-16:Register block parameters dialog boxXilinx Development System ReinterpretXilinx System Generator v2.1 Reference Guide Block Parameters Dialog box Serial to ParallelXilinx Blocks Basic ElementsBlock Parameters Dialog Box Block InterfaceXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areSlice Set Valid BitBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-21:Slice block operation Xilinx Development SystemBasic Elements SyncXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-23:Sync block use Xilinx Blocks Block Parameters Dialog BoxFigure 3-26:Sync block parameters dialog box Basic ElementsXilinx Development System Up SampleXilinx System Generator v2.1 Reference Guide Xilinx Blocks Block Parameters Dialog BoxFigure 3-29:Up Sample block parameters dialog box Basic ElementsConvolutional Encoder CommunicationBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box CommunicationXilinx LogiCORE Xilinx BlocksXilinx System Generator v2.1 Reference Guide DepunctureFigure 3-32:Example of Depuncture block use Xilinx Development SystemBlock Parameters Dialog Box Interleaver DeinterleaverXilinx Blocks CommunicationXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Block Parameters Dialog Box Block InterfaceXilinx LogiCORE Xilinx BlocksXilinx Development System PunctureXilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box RS DecoderXilinx Blocks Figure 3-38:Puncture block parameters dialog boxXilinx System Generator v2.1 Reference Guide Block InterfaceThe port descriptions are Xilinx Development SystemCommunication Block Parameters Dialog BoxXilinx Blocks Xilinx Development System g x = ∏ x –ahxGS + i i =Xilinx System Generator v2.1 Reference Guide Latency RS EncoderXilinx LogiCore Xilinx Blocksc x = g x ⋅ i g x = x –ai x –ai + 1 . . . . x –ai + 2tg x = x –a0 x –a1 x –a2 . . . . x –a15 Xilinx System Generator v2.1 Reference GuideCommunication Block InterfaceXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxParameters speciﬁc to the RS Encoder block are Xilinx Development SystemCommunication g x = ∏ x –ahxGS + i i =Xilinx Blocks Latency Viterbi DecoderXilinx LogiCore Xilinx System Generator v2.1 Reference GuideCommunication Block InterfaceBlock Parameters Dialog Box Xilinx Development System Xilinx LogiCoreXilinx System Generator v2.1 Reference Guide Figure 3-46:Pipelined decimator and interpolator Block InterfaceXilinx Blocks Xilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-47:CIC block parameters dialog boxXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-49:DDS block parameters dialog box Xilinx Development SystemXilinx Blocks X k = ∑ xmW N mkXilinx LogiCORE Block Interface W N = eBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block TimingFigure 3-51 FFT Timing Diagram Xilinx LogiCORE Figure 3-52:FFT Timing CharacteristicsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks yn = ∑ hixn –iBlock Interface Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-53:FIR block parameters dialog box Xilinx Development SystemAccumulator MathMath Xilinx LogiCOREXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areBlock Parameters Dialog Box AddSubXilinx LogiCORE Xilinx BlocksBlock Parameters Dialog Box CMultXilinx System Generator v2.1 Reference Guide Figure 3-56:CMult block parameters dialog boxXilinx LogiCORE InverterXilinx Blocks MathBlock Parameters Dialog Box LogicalXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks Figure 3-58:Logical block parameters dialog boxBlock Parameters Dialog Box MultXilinx System Generator v2.1 Reference Guide Xilinx Development SystemMath Xilinx LogiCOREXilinx Blocks Relational NegateBlock Parameters Dialog Box Xilinx LogiCOREXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks MathShift ScaleBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box SineCosineXilinx Blocks Figure 3-64:Shift block parameters dialog boxXilinx LogiCORE Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the SineCosine block areLatency Using Block ThresholdXilinx Blocks Maximum CoreMATLAB I/O Enabled SubsystemsGateway Blocks Block Parameters Dialog BoxGateway In Enable AdapterMATLAB I/O Xilinx BlocksXilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway In block are MATLAB I/O Gateway OutXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway Out block are Clear Quantization Error Quantization Error BlocksQuantization Error DisplayDual Port RAM MemoryBlock Interface Xilinx System Generator v2.1 Reference GuideFigure 3-70:Illustration of write modes MemoryXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxParameters speciﬁc to the block are Xilinx Development SystemXilinx LogiCORE log 2dXilinx Blocks DepthBlock Parameters Dialog Box FIFOXilinx System Generator v2.1 Reference Guide Figure 3-72:FIFO block parameters dialog boxMemory Xilinx LogiCOREXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-73:ROM block parameters dialog box Xilinx Development Systemlog 2d Xilinx LogiCOREXilinx Blocks DepthBlock Interface Single Port RAMXilinx System Generator v2.1 Reference Guide Xilinx Development SystemMemory Block Parameters Dialog BoxXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-75:Illustration of write modes log 2d Xilinx LogiCOREXilinx Blocks MemoryMealy State Machine State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks State MachineBlock Parameters Dialog Box Moore State MachineXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideState Machine Figure 3-80:Moore State Machine block diagramXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxFigure 3-82:Construction of Next State and Output matrices Xilinx Development SystemXilinx LogiCORE Registered Mealy State MachineXilinx Blocks State MachineXilinx Development System Xilinx System Generator v2.1 Reference GuideState Machine Block Parameters Dialog BoxXilinx Blocks width = k + o N = depth × width = k + o2k + depth = 2k 2i = 2k +Xilinx LogiCORE Xilinx System Generator v2.1 Reference GuideState Machine Registered Moore State MachineXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideN s = ds × ws = k 2k + ds = 2k 2i = 2k +Block Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide Xilinx LogiCOREwhere Xilinx Development SystemUsing the System Generator installer Chapter System Generator Software FeaturesSystem Generator Software Features >>setupInstalled System Generator directory Using Black BoxesA Black Box Example Xilinx System Generator v2.1 Reference GuideBlack Box window Using Black BoxesSystem Generator Software Features Figure 4-1:Output of example black box functionIncorporating mixed language black boxes Use of mixed language projectsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemFigure 4-2:Black Box block parameters dialog box Use of mixed language projectsSystem Generator Software Features Data Rate, Set ‘FAST’ Attribute Tips for creating a high performance designXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUsing the System Generator Constraints Files Using the System Generator Constraints FilesSystem Clock Period Multicycle Path ConstraintsExample for showing constraints use IOB Timing and Placement ConstraintsXilinx System Generator v2.1 Reference Guide Figure 4-4:Example of a multirate designUsing the System Generator Constraints Files System Generator Software FeaturesConstraints Files Important IssuesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Files automatically created by System GeneratorFiles automatically created by System Generator Xilinx Development System ∙sysgen.log - log ﬁleXilinx System Generator v2.1 Reference Guide Using the Xilinx Software Chapter Using the Xilinx SoftwareXilinx ISE 4.1i Project Navigator Opening a System Generator projectXilinx Development System Implementing your designXilinx System Generator v2.1 Reference Guide Xilinx ISE 4.1i Project Navigator Using the Xilinx SoftwareXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 5-6:Properties of simulation process Using an EDIF software flow Using an EDIF software ﬂowSimulation Compiling your IPXilinx Development System MXE librariesXilinx System Generator v2.1 Reference Guide Using the Xilinx Software Xilinx software tools resourcesXilinx software tools resources Demonstration designs Chapter Auxiliary FilesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemAuxiliary Files Perl scripts>> demo perl <scriptname> -hXilinx Development System Xilinx System Generator v2.1 Reference Guide