Xilinx Blocks
Block Parameters Dialog Box
The Addressable Shift Register Block Parameters Dialog Box can be invoked by
Figure
Parameters specific to the Addressable Shift Register block are:
∙Infer Maximum Latency (depth) using Address Port Width: you can choose to allow the block to automatically determine the depth or maximum latency of the
∙Maximum Latency (depth): In the case thaqt the maximum latency is not inferred (previous option), the maximum latency can be set explicitly. It must be a positive integer.
∙Allow Additional Hardware in Certain
∙Use Enable Port: when checked, the optional enable port is activated.
Other parameters used by this block are explained in the Common Parameters section of the previous chapter.
Xilinx LogiCORE
The block always uses the Xilinx LogiCORE
The core datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\ram_shift.pdf
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