Xilinx V2.1 manual Xilinx LogiCORE, Addressable Shift Register block parameters dialog box

Xilinx Blocks

Block Parameters Dialog Box

The Addressable Shift Register Block Parameters Dialog Box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-2: Addressable Shift Register block parameters dialog box

Parameters specific to the Addressable Shift Register block are:

∙Infer Maximum Latency (depth) using Address Port Width: you can choose to allow the block to automatically determine the depth or maximum latency of the shift-register based on the bit-width of the address port.

∙Maximum Latency (depth): In the case thaqt the maximum latency is not inferred (previous option), the maximum latency can be set explicitly. It must be a positive integer.

∙Allow Additional Hardware in Certain Rate-Change Cases: several rate-change conditions require the use of extra hardware beyond that used by the IP core to make it compliant with the Simulink simulation output. A rate-change condition will be detected if the address and data rates differ and the address port is running at a non-system rate. Choosing this parameter allows additonal hardware to be used in these cases.

∙Use Enable Port: when checked, the optional enable port is activated.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE Ram-based Shift Register V5.0. When the Generate Core parameter is checked, the Use Placement Information parameter provides the option of generating the core as a Relationally Placed Macro (RPM) or as unplaced logic.

The core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\ram_shift.pdf

Basic Elements 27