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Xilinx V2.1 Logical, Block Parameters Dialog Box, Xilinx LogiCORE, Xilinx Development System

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Logical

Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-57: Inverter block parameters dialog box

Parameters used by this block are explained in the Common Parameters section of the previous chapter of the Reference Guide.

Xilinx LogiCORE

The Inverter block uses the Xilinx LogiCORE Bus Gate V5.0 if the Implement with Xilinx Smart-IP Core parameter is checked and the input data width is between 1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL module.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\bus_gate.pdf

Logical

The Xilinx Logical block performs a bit-wise logical operation on 2, 3, or 4 ﬁxed point numbers. Operands are aligned at their respective binary points, zero padded, and sign extended as necessary. The logical operation is performed and produced at the output port.

The block can be implemented either as a Xilinx LogiCORE or as a synthesizable VHDL module. If you build a tree of logical gates, it is typically better to choose the synthesizable implementation so that

logic optimization can be applied during synthesis and mapping.

86	Xilinx Development System

Image 86

Xilinx V2.1 manual Logical, Block Parameters Dialog Box, Xilinx LogiCORE, Xilinx System Generator v2.1 Reference Guide

Contents

Using the Xilinx Software Auxiliary Files Printed in U.S.AXilinx Blocks System Generator Software Features Xilinx System Generator v2.1 forXilinx System Generator v2.1 Reference Guide Manual ContentsAbout This Manual Xilinx Development SystemDescription/URL Additional ResourcesResource >> cd <your $MATLAB home directory> ConventionsTypographical Xilinx System Generator v2.1 Reference GuideIntroduction ContentsChapter Chapter 2 Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter 6 Auxiliary Files Chapter 4 System Generator Software FeaturesChapter 5 Using the Xilinx Software Xilinx System Generator v2.1 Reference Guide Chapter IntroductionIndustry and Product Overview Xilinx Development SystemIntroduction System GeneratorSystem Level Modeling with System Generator System GeneratorXilinx Development System The System Generator Design FlowXilinx System Generator v2.1 Reference Guide MATLAB Environment The System Generator Design FlowLibrary SimulinkXilinx Development System Arithmetic Data TypesXilinx System Generator v2.1 Reference Guide Hardware Handshaking Hardware HandshakingMultirate Systems IntroductionXilinx System Generator v2.1 Reference Guide Bit-Trueand Cycle-TrueModelingAutomatic Testbench Generation Xilinx Development SystemChapter Xilinx Blockset Overview What is a Xilinx Block?What is a Xilinx Block? Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide The Nature of Signals in the Xilinx BlocksetThe Block Parameters Dialog Box Xilinx Development SystemPort Data Types The Nature of Signals in the Xilinx BlocksetValid and Invalid Data Xilinx Blockset OverviewXilinx Development System Licensed CoresXilinx System Generator v2.1 Reference Guide Common Options in Block Parameters Dialog Box Common Options in Block Parameters Dialog BoxXilinx LogiCORE Versions Xilinx Blockset OverviewImplement with Xilinx Smart-IP Core if possible Use Placement Information for CoreArithmetic Type Generate CoreOverﬂow and Quantization PrecisionNumber of Bits Override with DoublesXilinx System Generator v2.1 Reference Guide Sample PeriodUse Explicit Sample Period Xilinx Development SystemSystem Generator Chapter Xilinx BlocksBasic Elements Xilinx Blocks∙Target Directory Block Parameters Dialog Box∙Xilinx Product Family ∙System Clock Period∙Generate Cores ∙Global Clock Enable and Global Clear∙Override with Doubles ∙Generate buttonXilinx System Generator v2.1 Reference Guide Addressable Shift RegisterBlock Interface Xilinx Development SystemXilinx Blocks Xilinx LogiCOREBlock Parameters Dialog Box Basic ElementsBlock Parameters Dialog Box Black BoxIncorporating mixed language black boxes Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx BlocksFigure 3-3:Black Box block parameters dialog box Block Parameters Dialog Box ConcatBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box ConstantConvert Xilinx BlocksXilinx System Generator v2.1 Reference Guide CounterBlock Parameters Dialog Box Figure 3-7:Convert block parameters dialog boxXilinx Blocks Basic ElementsFigure 3-8:Counter block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box DelayXilinx LogiCORE Xilinx BlocksFigure 3-11:Down sample circuit behavior Down SampleXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Get Valid BitBlock Parameters Dialog Box Basic ElementsXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-13 Mux block parameters dialog boxXilinx Blocks Parallel to SerialBlock Interface Basic ElementsXilinx System Generator v2.1 Reference Guide RegisterBlock Parameters Dialog Box Xilinx Development SystemXilinx Blocks Block InterfaceBlock Parameters Dialog Box Figure 3-16:Register block parameters dialog boxXilinx Development System ReinterpretXilinx System Generator v2.1 Reference Guide Xilinx Blocks Serial to ParallelBlock Parameters Dialog box Basic ElementsXilinx System Generator v2.1 Reference Guide Block InterfaceBlock Parameters Dialog Box Parameters speciﬁc to the block areBlock Parameters Dialog Box Set Valid BitSlice Xilinx BlocksFigure 3-21:Slice block operation Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBasic Elements SyncXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-23:Sync block use Figure 3-26 Sync block parameters dialog box Block Parameters Dialog BoxXilinx Blocks Basic ElementsXilinx Development System Up SampleXilinx System Generator v2.1 Reference Guide Figure 3-29:Up Sample block parameters dialog box Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlock Interface CommunicationConvolutional Encoder Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE CommunicationBlock Parameters Dialog Box Xilinx BlocksFigure 3-32:Example of Depuncture block use DepunctureXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Interleaver DeinterleaverBlock Parameters Dialog Box CommunicationXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Xilinx LogiCORE Block InterfaceBlock Parameters Dialog Box Xilinx BlocksXilinx Development System PunctureXilinx System Generator v2.1 Reference Guide Xilinx Blocks RS DecoderBlock Parameters Dialog Box Figure 3-38:Puncture block parameters dialog boxThe port descriptions are Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemCommunication Block Parameters Dialog BoxXilinx Blocks Xilinx Development System g x = ∏ x –ahxGS + i i =Xilinx System Generator v2.1 Reference Guide Xilinx LogiCore RS EncoderLatency Xilinx Blocksg x = x –a0 x –a1 x –a2 . . . . x –a15 g x = x –ai x –ai + 1 . . . . x –ai + 2tc x = g x ⋅ i Xilinx System Generator v2.1 Reference GuideCommunication Block InterfaceXilinx Blocks Parameters speciﬁc to the RS Encoder block are Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemCommunication g x = ∏ x –ahxGS + i i =Xilinx Blocks Xilinx LogiCore Viterbi DecoderLatency Xilinx System Generator v2.1 Reference GuideCommunication Block InterfaceBlock Parameters Dialog Box Xilinx Development System Xilinx LogiCoreXilinx System Generator v2.1 Reference Guide Figure 3-46:Pipelined decimator and interpolator Block InterfaceXilinx Blocks Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-47:CIC block parameters dialog boxXilinx Blocks Figure 3-49:DDS block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks X k = ∑ xmW N mkXilinx LogiCORE Block Parameters Dialog Box W N = eBlock Interface Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block TimingFigure 3-51 FFT Timing Diagram Xilinx System Generator v2.1 Reference Guide Figure 3-52:FFT Timing CharacteristicsXilinx LogiCORE Xilinx Development SystemXilinx Blocks yn = ∑ hixn –iBlock Interface Figure 3-53:FIR block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemMath MathAccumulator Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Parameters speciﬁc to the block areXilinx LogiCORE AddSubBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide CMultBlock Parameters Dialog Box Figure 3-56:CMult block parameters dialog boxXilinx Blocks InverterXilinx LogiCORE MathXilinx LogiCORE LogicalBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block Parameters Dialog BoxXilinx LogiCORE Figure 3-58:Logical block parameters dialog boxXilinx System Generator v2.1 Reference Guide MultBlock Parameters Dialog Box Xilinx Development SystemMath Xilinx LogiCOREXilinx Blocks Block Parameters Dialog Box NegateRelational Xilinx LogiCOREXilinx Blocks Block Parameters Dialog BoxXilinx LogiCORE MathBlock Parameters Dialog Box ScaleShift Xilinx System Generator v2.1 Reference GuideXilinx Blocks SineCosineBlock Parameters Dialog Box Figure 3-64:Shift block parameters dialog boxXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Parameters speciﬁc to the SineCosine block areXilinx Blocks ThresholdLatency Using Block Maximum CoreGateway Blocks Enabled SubsystemsMATLAB I/O Block Parameters Dialog BoxMATLAB I/O Enable AdapterGateway In Xilinx BlocksXilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway In block are MATLAB I/O Gateway OutXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway Out block are Quantization Error Quantization Error BlocksClear Quantization Error DisplayBlock Interface MemoryDual Port RAM Xilinx System Generator v2.1 Reference GuideFigure 3-70:Illustration of write modes MemoryXilinx Blocks Parameters speciﬁc to the block are Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks log 2dXilinx LogiCORE DepthXilinx System Generator v2.1 Reference Guide FIFOBlock Parameters Dialog Box Figure 3-72:FIFO block parameters dialog boxMemory Xilinx LogiCOREXilinx Blocks Figure 3-73:ROM block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Xilinx LogiCORElog 2d DepthXilinx System Generator v2.1 Reference Guide Single Port RAMBlock Interface Xilinx Development SystemMemory Block Parameters Dialog BoxXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-75:Illustration of write modes Xilinx Blocks Xilinx LogiCORElog 2d MemoryXilinx System Generator v2.1 Reference Guide State MachineMealy State Machine Xilinx Development SystemState Machine Xilinx BlocksXilinx LogiCORE Moore State MachineBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideState Machine Figure 3-80:Moore State Machine block diagramXilinx Blocks Figure 3-82:Construction of Next State and Output matrices Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Registered Mealy State MachineXilinx LogiCORE State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemState Machine Block Parameters Dialog BoxXilinx Blocks Xilinx LogiCORE depth = 2k 2i = 2k +width = k + o N = depth × width = k + o2k + Xilinx System Generator v2.1 Reference GuideState Machine Registered Moore State MachineXilinx Blocks Xilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box ds = 2k 2i = 2k +N s = ds × ws = k 2k + Xilinx Blockswhere Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Chapter System Generator Software FeaturesUsing the System Generator installer >>setupA Black Box Example Using Black BoxesInstalled System Generator directory Xilinx System Generator v2.1 Reference GuideSystem Generator Software Features Using Black BoxesBlack Box window Figure 4-1:Output of example black box functionXilinx System Generator v2.1 Reference Guide Use of mixed language projectsIncorporating mixed language black boxes Xilinx Development SystemFigure 4-2:Black Box block parameters dialog box Use of mixed language projectsSystem Generator Software Features Xilinx System Generator v2.1 Reference Guide Tips for creating a high performance designData Rate, Set ‘FAST’ Attribute Xilinx Development SystemSystem Clock Period Using the System Generator Constraints FilesUsing the System Generator Constraints Files Multicycle Path ConstraintsXilinx System Generator v2.1 Reference Guide IOB Timing and Placement ConstraintsExample for showing constraints use Figure 4-4:Example of a multirate designSystem Generator Software Features Using the System Generator Constraints FilesXilinx System Generator v2.1 Reference Guide Important IssuesConstraints Files Xilinx Development SystemSystem Generator Software Features Files automatically created by System GeneratorFiles automatically created by System Generator Xilinx Development System ∙sysgen.log - log ﬁleXilinx System Generator v2.1 Reference Guide Xilinx ISE 4.1i Project Navigator Chapter Using the Xilinx SoftwareUsing the Xilinx Software Opening a System Generator projectXilinx Development System Implementing your designXilinx System Generator v2.1 Reference Guide Using the Xilinx Software Xilinx ISE 4.1i Project NavigatorXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 5-6:Properties of simulation process Simulation Using an EDIF software ﬂowUsing an EDIF software flow Compiling your IPXilinx Development System MXE librariesXilinx System Generator v2.1 Reference Guide Using the Xilinx Software Xilinx software tools resourcesXilinx software tools resources Xilinx System Generator v2.1 Reference Guide Chapter Auxiliary FilesDemonstration designs Xilinx Development System>> demo Perl scriptsAuxiliary Files perl <scriptname> -hXilinx System Generator v2.1 Reference Guide Xilinx Development System