Xilinx V2.1 manual The System Generator Design Flow, Library, MATLAB Environment, Simulink, Xilinx

Introduction

The System Generator design flow is shown in the following figure.

Library			MATLAB Environment
(including
Xilinx
Blockset)			Simulink
Simulation	Input	System Model
			Output
		+	Z–1
			k
including			Simulation
S-functions
			Data
Synthesis
ENTITY mult IS		System Generator
GENERIC(w:		Code Generation Software
PORT(a,b:IN		- map to IP libraries
PORT(y:OUT		- control signals
END ENTITY		- VHDL design
...
		- HDL testbench
		- constraints
		- simulation scripts, project files

	Core	Xilinx
VHDL		DesignTools
	Parameters
		Environment
Synthesis	CORE
Compiler	Generator	Test
EDIF		Vectors
FPGA	EDIF + Timing	Logic
Place & Route		Simulator
Bit stream		Pass/Fail

Figure 1-1: System Generator design flow diagram

The Xilinx Blockset is accessible in the Simulink library browser, and elements can be freely combined with other Simulink elements. Only those subsystems denoted as Xilinx black boxes, and blocks and subsystems consisting of blocks from the Xilinx Blockset are translated by System Generator into a hardware realization. The generation process is controlled from the System Generator block found in the Xilinx Blockset Basic Elements library. The System Generator parameterization GUI allows the user to choose the target FPGA device, target system clock period, and other implementation options.

System Generator translates the Simulink model into a hardware realization by mapping Xilinx Blockset elements into IP library modules, inferring control signals and circuitry from system parameters (e.g. sample periods), and converting the

The System Generator Design Flow 11