Xilinx V2.1 manual Arithmetic Type, Implement with Xilinx Smart-IP Core if possible, Generate Core

Xilinx System Generator v2.1 Reference Guide

specific parameters are described in the specific block documentation in the next chapter.

The remainder of the parameters in each block’s parameters dialog box are common to most blocks. These common parameters are described below.

Arithmetic Type

In the Type field of the block parameters dialog box, you can choose unsigned or signed (two’s complement) as the datatype of the output signal.

Implement with Xilinx Smart-IP™Core (if possible)

This checkbox (sometimes referred to as the Use Core checkbox) asks the software to instantiate a core in the generated VHDL. If you do not select this checkbox, the software will instead create synthesizable VHDL.

Selecting this option does not guarantee that a Xilinx LogiCORE will be used. If the parameters for your block are such that a core cannot be generated, synthesizable VHDL will be generated instead. The System Generator software determines this at code generation time.

Generate Core

When the Generate Core checkbox is selected, the Xilinx CORE Generator will be invoked during System Generator code generation. If Generate Core is not selected, a Xilinx LogiCORE will not be generated, and if the core doesn’t already exist in your project directory, subsequently running the Xilinx Implementation tools will produce an error.

If you select Implement with Xilinx Smart-IP Core but do not select Generate Core, you will be able to simulate your generated VHDL because (1) a core will be instantiated in the VHDL, and (2) the behavioral VHDL models will be available for a simulator to use. However, you will not be able to complete implementation into a Xilinx FPGA until you have also generated the core.

In some blocks, only the Generate Core option is available. If the Implement with Smart IP-Coreoption is not available, only a core implementation is available from the System Generator, but no synthesizable VHDL implementation.

Use Placement Information for Core

If Generate Core is selected,the generated core includes relative placement information. This generally results in a faster implementation. Because the placement is constrained by this information, it can sometimes hinder the place and route software.

Latency

Many elements in the Xilinx Blockset have a latency option. This defines the number of sample periods by which the block’s output is delayed. One sample period may correspond to multiple clock cycles in the corresponding FPGA implementation (for example, when the hardware is overclocked with respect to the Simulink model). System Generator v2.1 does not perform extensive pipelining; additional latency is usually implemented as a shift register on the output of the block.

20 Xilinx Development System