Xilinx System Generator v2.1 Reference Guide

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The RS Encoder block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details.

Latency

The RS Encoder has a 6 sample period latency for CCSDS code specification and a 4 sample period latency for all other specifications.

Xilinx LogiCore

The RS Encoder block uses Xilinx LogiCORE RS Encoder v2.0.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\rs_encoder_v2_0\ doc\rs_encoder.pdf

This is a licensed core, available for purchase on the Xilinx web site at:

http://www.xilinx.com/ipcenter/reed_solomon

Viterbi Decoder

The Xilinx Viterbi Decoder block is used for decoding convolutionally encoded data. The first step in decoding is to assess the cost of the incoming data against all possible data input combinations. Either the Hamming or Euclidean metric is used to determine the cost. The cost determines the distance to each state in the Viterbi trellis. The second and final decoding step is to trace backwards through the trellis and determine the optimal path. The

length of the trace through the trellis is determined from the traceback length parameter.

The Viterbi Decoder has a lower error rate when given optimal convolution codes. On the Convolutional Encoder, the convolution codes are used to select which bits in the constraint register are XORed to generate the encoded output. The convolution codes must match those on the corresponding convolutional encoder. When using sub- optimal codes, the opposite path has the same cost as the desired path in the Viterbi trellis and decoding errors will result. The following table provides a list of optimal codes. The constraint length is inferred from the length of the convolution code.

Constraint

Optimal convolution codes for

Optimal convolution codes for

length

decoding 1/2 rate encoders

decoding 1/3 rate encoders

3

111,101

111,111,101

 

 

 

4

111,1011

111,1011,1101

 

 

 

5

11111,11011

11111,11011,10101

 

 

 

6

101111, 110101

101111, 110101,111001

 

 

 

7

1001111,1010111

1001111,1010111,1101101

 

 

 

8

11101111, 10011011

11101111, 10011011, 10101001

 

 

 

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Xilinx V2.1 manual Viterbi Decoder, Latency
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V2.1 specifications

Xilinx V2.1 is a notable iteration in the series of versatile and robust Field-Programmable Gate Arrays (FPGAs) developed to cater to a wide range of applications. Launched to provide enhancements in performance and flexibility, V2.1 embodies sophisticated technologies and features that stand out in the electronics industry.

One of the primary features of Xilinx V2.1 is its improved processing power. The architecture has been optimized to support higher clock speeds and increased logic density, allowing for more complex designs to be implemented effectively. This boost in performance is facilitated by utilizing advanced silicon technologies, which significantly reduce power consumption while maximizing efficiency.

Another significant characteristic of Xilinx V2.1 is its enhanced I/O (Input/Output) capabilities. The device supports a variety of industry-standard interfaces, which include PCI Express, SATA, and various serial communication protocols. Such adaptability ensures seamless integration into existing systems, providing engineers with the flexibility to adapt to various application requirements without the need for substantial redesign efforts.

Xilinx V2.1 also features improved scalability, making it a prime choice for applications that demand diverse performance levels. This device supports an array of configurations and can be used in small-scale projects as well as in larger, more demanding environments requiring extensive resources. This scalability is further aided by support for multiple development platforms, enabling rapid prototyping and simplifying the design process.

Security is increasingly becoming a priority in digital design, and Xilinx V2.1 addresses this concern via hardware security features. It includes enhanced encryption protocols and secure boot functionalities, which help protect intellectual property and sensitive data from unauthorized access.

Additionally, the integration of advanced DSP (Digital Signal Processing) blocks allows Xilinx V2.1 to efficiently handle data-intensive tasks such as video processing and real-time signal analysis. These capabilities make it suitable for applications in telecommunications, automotive systems, and industrial automation.

Xilinx V2.1 also benefits from a rich development environment, including robust software tools that facilitate design entry, simulation, and verification. The support for industry-standard programming languages like VHDL and Verilog simplifies the development process, enabling engineers to design complex systems more efficiently.

In summary, Xilinx V2.1 stands out due to its impressive combination of high performance, flexibility, scalability, security, and comprehensive development support. These features make it a valuable asset for engineers and developers looking to innovate across various sectors, from telecommunications and automotive to industrial applications.
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