Xilinx V2.1 System Generator Software Features, Using the System Generator Constraints Files

System Generator Software Features

The ce2_group contains the blocks operating at twice the system period, i.e., the input register and the up sampler. Here are the corresponding constraints.

#ce2_group and inner group constraint INST "InReg" TNM = "ce2_group";

INST "Up_Sample" TNM = "ce2_group";

TIMESPEC "TS_ce2_group_to_ce2_group" = FROM "ce2_group" TO "ce2_group" "TS_clk" * 2;

The ce3_group operates at three times the system period. It contains the down sampler and the output register, and its constraints are the following.

#ce3_group and inner group constraint INST "Down_Sample" TNM = "ce3_group"; INST "OutReg" TNM = "ce3_group";

TIMESPEC "TS_ce3_group_to_ce3_group" = FROM "ce3_group" TO "ce3_group" "TS_clk" * 3;

Group to group constraints establish the relative speeds of the groups. Here are the constraints that relate the speed of ce2_group to ce1_group.

# Group-to-group constraints

TIMESPEC "TS_ce1_group_to_ce2_group" = FROM "ce1_group" TO "ce2_group" "TS_clk" * 1;

TIMESPEC "TS_ce1_group_to_ce3_group" = FROM "ce1_group" TO "ce3_group" "TS_clk" * 1;

TIMESPEC "TS_ce2_group_to_ce1_group" = FROM "ce2_group" TO "ce1_group" "TS_clk" * 1;

TIMESPEC "TS_ce2_group_to_ce3_group" = FROM "ce2_group" TO "ce3_group" "TS_clk" * 2;

TIMESPEC "TS_ce3_group_to_ce1_group" = FROM "ce3_group" TO "ce1_group" "TS_clk" * 1;

TIMESPEC "TS_ce3_group_to_ce2_group" = FROM "ce3_group" TO "ce2_group" "TS_clk" * 2;

Port timing requirements can be set in the parameter dialog boxes for Gateway In and Out blocks. These requirements are translated into port constraints like those shown below. In this example, the 3-bit DIN input is constrained to operate at its gateway’s sample rate (corresponding to a period of 20 ns). The 'FAST' attributes indicate that the ports should be implemented using hardware resources that reduce delay. (The delay is reduced, but at a cost of increased noise and power consumption.) The Din_valid lines constrain the companion valid signal that accompanies DIN. For more information concerning valid signals, see the Hardware Handshaking section.

# Offset in constraints

NET "Din<0>" OFFSET = IN : 20.0 : BEFORE "clk";

NET "Din<1>" OFFSET = IN : 20.0 : BEFORE "clk";

NET "Din<2>" OFFSET = IN : 20.0 : BEFORE "clk";

NET "Din_valid" OFFSET = IN : 20.0 : BEFORE "clk";

NET "Din<0>" FAST;

NET "Din<1>" FAST;

NET "Din<2>" FAST;

NET "Din_valid" FAST;

Checking the Specify IOB Location Constraints option for a Gateway In or Gateway Out block allows port locations to be specified. The locations must be entered as a

Using the System Generator Constraints Files 135