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Xilinx V2.1 manual Xilinx System Generator v2.1 Reference Guide, Xilinx Development System

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Xilinx System Generator v2.1 Reference Guide

Figure 3-34: Forney convolutional interleaver with a constant difference between consecutive branches

When the block is in deinterleaver mode, the input data sampled on the DIN port is multiplexed into and out of B shift registers onto the DOUT port using two (synchronized) commutator arms. Branch 0 will have a shift register of length (B-1)*L. Branch (B-1) shall have a shift register length of zero.

Figure 3-35: Forney convolutional deinterleaver with a constant difference between consecutive branches

56	Xilinx Development System

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Xilinx V2.1 manual Xilinx System Generator v2.1 Reference Guide, Xilinx Development System

Contents

Printed in U.S.A Xilinx Blocks System Generator Software FeaturesUsing the Xilinx Software Auxiliary Files Xilinx System Generator v2.1 forManual Contents About This ManualXilinx System Generator v2.1 Reference Guide Xilinx Development SystemDescription/URL Additional ResourcesResource Conventions Typographical>> cd <your $MATLAB home directory> Xilinx System Generator v2.1 Reference GuideContents ChapterIntroduction Chapter 2 Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter 6 Auxiliary Files Chapter 4 System Generator Software FeaturesChapter 5 Using the Xilinx Software Chapter Introduction Industry and Product OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator System Level Modeling with System GeneratorIntroduction System GeneratorXilinx Development System The System Generator Design FlowXilinx System Generator v2.1 Reference Guide The System Generator Design Flow LibraryMATLAB Environment SimulinkXilinx Development System Arithmetic Data TypesXilinx System Generator v2.1 Reference Guide Hardware Handshaking Multirate SystemsHardware Handshaking IntroductionBit-Trueand Cycle-TrueModeling Automatic Testbench GenerationXilinx System Generator v2.1 Reference Guide Xilinx Development SystemWhat is a Xilinx Block? What is a Xilinx Block?Chapter Xilinx Blockset Overview Xilinx Blockset OverviewThe Nature of Signals in the Xilinx Blockset The Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemThe Nature of Signals in the Xilinx Blockset Valid and Invalid DataPort Data Types Xilinx Blockset OverviewXilinx Development System Licensed CoresXilinx System Generator v2.1 Reference Guide Common Options in Block Parameters Dialog Box Xilinx LogiCORE VersionsCommon Options in Block Parameters Dialog Box Xilinx Blockset OverviewUse Placement Information for Core Arithmetic TypeImplement with Xilinx Smart-IP Core if possible Generate CorePrecision Number of BitsOverﬂow and Quantization Override with DoublesSample Period Use Explicit Sample PeriodXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter Xilinx Blocks Basic ElementsSystem Generator Xilinx BlocksBlock Parameters Dialog Box ∙Xilinx Product Family∙Target Directory ∙System Clock Period∙Global Clock Enable and Global Clear ∙Override with Doubles∙Generate Cores ∙Generate buttonAddressable Shift Register Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx LogiCORE Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlack Box Incorporating mixed language black boxesBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideBasic Elements Xilinx BlocksFigure 3-3:Black Box block parameters dialog box Concat Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideConstant ConvertBlock Parameters Dialog Box Xilinx BlocksCounter Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-7:Convert block parameters dialog boxXilinx Blocks Basic ElementsBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-8:Counter block parameters dialog box Xilinx Development SystemDelay Xilinx LogiCOREBlock Parameters Dialog Box Xilinx BlocksDown Sample Xilinx System Generator v2.1 Reference GuideFigure 3-11:Down sample circuit behavior Xilinx Development SystemGet Valid Bit Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Figure 3-13:Mux block parameters dialog boxParallel to Serial Block InterfaceXilinx Blocks Basic ElementsRegister Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Interface Block Parameters Dialog BoxXilinx Blocks Figure 3-16:Register block parameters dialog boxXilinx Development System ReinterpretXilinx System Generator v2.1 Reference Guide Serial to Parallel Block Parameters Dialog boxXilinx Blocks Basic ElementsBlock Interface Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areSet Valid Bit SliceBlock Parameters Dialog Box Xilinx BlocksBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-21:Slice block operation Xilinx Development SystemBasic Elements SyncXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-23:Sync block use Block Parameters Dialog Box Xilinx BlocksFigure 3-26:Sync block parameters dialog box Basic ElementsXilinx Development System Up SampleXilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box Xilinx BlocksFigure 3-29:Up Sample block parameters dialog box Basic ElementsCommunication Convolutional EncoderBlock Interface Xilinx System Generator v2.1 Reference GuideCommunication Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksDepuncture Xilinx System Generator v2.1 Reference GuideFigure 3-32:Example of Depuncture block use Xilinx Development SystemInterleaver Deinterleaver Block Parameters Dialog BoxXilinx Blocks CommunicationXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Block Interface Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksXilinx Development System PunctureXilinx System Generator v2.1 Reference Guide RS Decoder Block Parameters Dialog BoxXilinx Blocks Figure 3-38:Puncture block parameters dialog boxBlock Interface Xilinx System Generator v2.1 Reference GuideThe port descriptions are Xilinx Development SystemCommunication Block Parameters Dialog BoxXilinx Blocks Xilinx Development System g x = ∏ x –ahxGS + i i =Xilinx System Generator v2.1 Reference Guide RS Encoder LatencyXilinx LogiCore Xilinx Blocksg x = x –ai x –ai + 1 . . . . x –ai + 2t c x = g x ⋅ ig x = x –a0 x –a1 x –a2 . . . . x –a15 Xilinx System Generator v2.1 Reference GuideCommunication Block InterfaceXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the RS Encoder block are Xilinx Development SystemCommunication g x = ∏ x –ahxGS + i i =Xilinx Blocks Viterbi Decoder LatencyXilinx LogiCore Xilinx System Generator v2.1 Reference GuideCommunication Block InterfaceBlock Parameters Dialog Box Xilinx Development System Xilinx LogiCoreXilinx System Generator v2.1 Reference Guide Figure 3-46:Pipelined decimator and interpolator Block InterfaceXilinx Blocks Block Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Figure 3-47:CIC block parameters dialog boxXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-49:DDS block parameters dialog box Xilinx Development SystemXilinx Blocks X k = ∑ xmW N mkXilinx LogiCORE W N = e Block InterfaceBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block TimingFigure 3-51 FFT Timing Diagram Figure 3-52:FFT Timing Characteristics Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks yn = ∑ hixn –iBlock Interface Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-53:FIR block parameters dialog box Xilinx Development SystemMath AccumulatorMath Xilinx LogiCOREBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the block areAddSub Block Parameters Dialog BoxXilinx LogiCORE Xilinx BlocksCMult Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-56:CMult block parameters dialog boxInverter Xilinx LogiCOREXilinx Blocks MathLogical Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks Figure 3-58:Logical block parameters dialog boxMult Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemMath Xilinx LogiCOREXilinx Blocks Negate RelationalBlock Parameters Dialog Box Xilinx LogiCOREBlock Parameters Dialog Box Xilinx LogiCOREXilinx Blocks MathScale ShiftBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideSineCosine Block Parameters Dialog BoxXilinx Blocks Figure 3-64:Shift block parameters dialog boxBlock Parameters Dialog Box Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Parameters speciﬁc to the SineCosine block areThreshold Latency Using BlockXilinx Blocks Maximum CoreEnabled Subsystems MATLAB I/OGateway Blocks Block Parameters Dialog BoxEnable Adapter Gateway InMATLAB I/O Xilinx BlocksXilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway In block are MATLAB I/O Gateway OutXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the Gateway Out block are Quantization Error Blocks Clear Quantization ErrorQuantization Error DisplayMemory Dual Port RAMBlock Interface Xilinx System Generator v2.1 Reference GuideFigure 3-70:Illustration of write modes MemoryXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideParameters speciﬁc to the block are Xilinx Development Systemlog 2d Xilinx LogiCOREXilinx Blocks DepthFIFO Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Figure 3-72:FIFO block parameters dialog boxMemory Xilinx LogiCOREXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-73:ROM block parameters dialog box Xilinx Development SystemXilinx LogiCORE log 2dXilinx Blocks DepthSingle Port RAM Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemMemory Block Parameters Dialog BoxXilinx Blocks Xilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 3-75:Illustration of write modes Xilinx LogiCORE log 2dXilinx Blocks MemoryState Machine Mealy State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemState Machine Xilinx BlocksMoore State Machine Block Parameters Dialog BoxXilinx LogiCORE Xilinx System Generator v2.1 Reference GuideState Machine Figure 3-80:Moore State Machine block diagramXilinx Blocks Block Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideFigure 3-82:Construction of Next State and Output matrices Xilinx Development SystemRegistered Mealy State Machine Xilinx LogiCOREXilinx Blocks State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemState Machine Block Parameters Dialog BoxXilinx Blocks depth = 2k 2i = 2k + width = k + o N = depth × width = k + o2k +Xilinx LogiCORE Xilinx System Generator v2.1 Reference GuideState Machine Registered Moore State MachineXilinx Blocks Xilinx System Generator v2.1 Reference Guide Xilinx Development Systemds = 2k 2i = 2k + N s = ds × ws = k 2k +Block Parameters Dialog Box Xilinx BlocksXilinx LogiCORE Xilinx System Generator v2.1 Reference Guidewhere Xilinx Development SystemChapter System Generator Software Features Using the System Generator installerSystem Generator Software Features >>setupUsing Black Boxes Installed System Generator directoryA Black Box Example Xilinx System Generator v2.1 Reference GuideUsing Black Boxes Black Box windowSystem Generator Software Features Figure 4-1:Output of example black box functionUse of mixed language projects Incorporating mixed language black boxesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemFigure 4-2:Black Box block parameters dialog box Use of mixed language projectsSystem Generator Software Features Tips for creating a high performance design Data Rate, Set ‘FAST’ AttributeXilinx System Generator v2.1 Reference Guide Xilinx Development SystemUsing the System Generator Constraints Files Using the System Generator Constraints FilesSystem Clock Period Multicycle Path ConstraintsIOB Timing and Placement Constraints Example for showing constraints useXilinx System Generator v2.1 Reference Guide Figure 4-4:Example of a multirate designSystem Generator Software Features Using the System Generator Constraints FilesImportant Issues Constraints FilesXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Files automatically created by System GeneratorFiles automatically created by System Generator Xilinx Development System ∙sysgen.log - log ﬁleXilinx System Generator v2.1 Reference Guide Chapter Using the Xilinx Software Using the Xilinx SoftwareXilinx ISE 4.1i Project Navigator Opening a System Generator projectXilinx Development System Implementing your designXilinx System Generator v2.1 Reference Guide Using the Xilinx Software Xilinx ISE 4.1i Project NavigatorXilinx Development System Xilinx System Generator v2.1 Reference GuideFigure 5-6:Properties of simulation process Using an EDIF software ﬂow Using an EDIF software flowSimulation Compiling your IPXilinx Development System MXE librariesXilinx System Generator v2.1 Reference Guide Using the Xilinx Software Xilinx software tools resourcesXilinx software tools resources Chapter Auxiliary Files Demonstration designsXilinx System Generator v2.1 Reference Guide Xilinx Development SystemPerl scripts Auxiliary Files>> demo perl <scriptname> -hXilinx System Generator v2.1 Reference Guide Xilinx Development System