Xilinx System Generator v2.1 Reference Guide

The division of the design into parts, and the speed at which each part must run, are specified in the constraints file using multicycle path constraints. The example below shows how this is done.

IOB Timing and Placement Constraints

When translated into hardware, System Generator’s Gateway In and Gateway Out blocks become input and output ports. The locations of these ports and the speeds at which they must operate can be entered in the Gateway In and Out configuration GUIs. Please see the descriptions of the Gateway In block and the Gateway Out block in the MATLAB I/O library section for more information.

Port location and speed are specified in the constraints file by IOB timing and placement constraints. The following example shows the details

Example for showing constraints use

Figure 4-4: Example of a multirate design

The up sampler doubles the sample rate, and the down sampler divides the sample rate by three. In this design, the system clock period is 10 ns (specified in the parameters dialog box for the System Generator block), so the clock periods are 10 ns for the FIR, 20 ns for the input register, and 30 ns for the output register. Shown below are the constraints that carry this information.

Here are the lines from the ucf file that indicate the system clock period is 10 ns.

#Global period constraint NET "clk" TNM_NET = "clk";

TIMESPEC "TS_clk" = PERIOD "clk" 10.0 ns HIGH 50 %;

To build the timing constraints, the blocks in the design are partitioned into timing groups. Two blocks are in the same timing group if and only if they run at the same sample rate. In this design the timing groups are named ce1_group, ce2_group, and ce3_group.

The FIR block runs at the system rate and therefore goes into the ce1_group. The logic used to generate clocks always runs at the system rate and is therefore in the ce1_group as well. The constraints for the ce1_group are the following.

#ce1_group and inner group constraint INST "FIR" TNM = "ce1_group";

INST "clock_driver_1" TNM = "ce1_group";

TIMESPEC "TS_ce1_group_to_ce1_group" = FROM "ce1_group" TO "ce1_group" "TS_clk" * 1;

134

Xilinx Development System

Page 133 Page 135
Page 134
Image 134
Xilinx V2.1 manual IOB Timing and Placement Constraints, Example for showing constraints use
Page 133 Page 135

V2.1 specifications

Xilinx V2.1 is a notable iteration in the series of versatile and robust Field-Programmable Gate Arrays (FPGAs) developed to cater to a wide range of applications. Launched to provide enhancements in performance and flexibility, V2.1 embodies sophisticated technologies and features that stand out in the electronics industry.

One of the primary features of Xilinx V2.1 is its improved processing power. The architecture has been optimized to support higher clock speeds and increased logic density, allowing for more complex designs to be implemented effectively. This boost in performance is facilitated by utilizing advanced silicon technologies, which significantly reduce power consumption while maximizing efficiency.

Another significant characteristic of Xilinx V2.1 is its enhanced I/O (Input/Output) capabilities. The device supports a variety of industry-standard interfaces, which include PCI Express, SATA, and various serial communication protocols. Such adaptability ensures seamless integration into existing systems, providing engineers with the flexibility to adapt to various application requirements without the need for substantial redesign efforts.

Xilinx V2.1 also features improved scalability, making it a prime choice for applications that demand diverse performance levels. This device supports an array of configurations and can be used in small-scale projects as well as in larger, more demanding environments requiring extensive resources. This scalability is further aided by support for multiple development platforms, enabling rapid prototyping and simplifying the design process.

Security is increasingly becoming a priority in digital design, and Xilinx V2.1 addresses this concern via hardware security features. It includes enhanced encryption protocols and secure boot functionalities, which help protect intellectual property and sensitive data from unauthorized access.

Additionally, the integration of advanced DSP (Digital Signal Processing) blocks allows Xilinx V2.1 to efficiently handle data-intensive tasks such as video processing and real-time signal analysis. These capabilities make it suitable for applications in telecommunications, automotive systems, and industrial automation.

Xilinx V2.1 also benefits from a rich development environment, including robust software tools that facilitate design entry, simulation, and verification. The support for industry-standard programming languages like VHDL and Verilog simplifies the development process, enabling engineers to design complex systems more efficiently.

In summary, Xilinx V2.1 stands out due to its impressive combination of high performance, flexibility, scalability, security, and comprehensive development support. These features make it a valuable asset for engineers and developers looking to innovate across various sectors, from telecommunications and automotive to industrial applications.
Top Page Image Contents