Xilinx Blocks
infer them in the generated VHDL. The block parameters dialog box can be invoked by
Figure 3-3: Black Box block parameters dialog box
Parameters specified as cell arrays (generic or parameter names, types, and values) permit several methods for entering data. You can specify your data directly in the dialog box as shown. You may also specify the cell arrays as MATLAB expressions.
This is useful if you have many elements in your cell arrays. Generic types can be any VHDL type. Parameter types can be any Verilog type.
The black box block parameters dialog box allows you to specify multiple clocks on a black box. To handle more than one clock, the System Generator must be told how fast each clock should run. To specify a clock’s speed, you must associate the clock to a port on the black box; the frequency of the clock is then the frequency of the signal passing through the port. System Generator allows more than one port to be associated to a clock, but all associated ports must have the same frequency.
Note - Constant inputs match any paired frequency.
For example, a black box with two ports (a fast input and a slow output) should have clocks called fast_clk and slow_clk with frequencies that match those of the
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