![Register](/images/new-backgrounds/55306/5530679x1.webp)
Xilinx System Generator v2.1 Reference Guide
Block Parameters Dialog Box
Figure
Parameters specific to the block are:
∙Output Order: Most significant word first or least significant word first. Word size is determined by the size of the input port.
∙Output Arithmetic Type: unsigned or signed
∙Number of Input Bits: Input width. Must match size of input port.
∙Number of Output Bits: Output width. Must divide Number of Input Bits evenly.
∙Binary Point: Output binary point location.
An error is reported when the number of output bits does not evenly divide the number of input bits.
The minimum latency of this block is 1.
Other parameters used by this block are explained in the Common Parameters section of the previous chapter.
The Parallel to Serial block does not use a Xilinx LogiCORE.
Register
The Xilinx Register block models a D flip
40 | Xilinx Development System |