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Xilinx V2.1 manual Fifo, Block Parameters Dialog Box, Xilinx System Generator v2.1 Reference Guide

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FIFO

Xilinx System Generator v2.1 Reference Guide

FIFO

The Xilinx FIFO block implements a First-In-First-Out memory queue.

Values presented at the module’s data-input port is written to the next available empty memory location when the write-enable input is one. The memory full status output port is assserted to one when no unused locations remain in the module’s internal memory. The percent full output port indicates the percentage of internal memory in use, represented with user-speciﬁed precision. By asserting the read-enable input port, data can be read out of the FFO via the data output port (dout) in the order in which they were written. The

memory-empty status output (empty) indicates that no more data reside in the memory.

The FIFO can be implemented either using distributed or block RAM. If distributed memory is selected, the maximum depth of the FIFO is 256. If block RAM is used, the maximum depth is 64K words.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink mode.

Figure 3-72: FIFO block parameters dialog box

Parameters speciﬁc to the FIFO block are:

∙Depth: speciﬁes the number of words that can be stored.

∙Bits of Precision to Use for Percent Full Signal: speciﬁes the number of bits that will be output from the %full port. The binary point for this unsigned output is always at the top of the word. Thus, if the Bits of Precision is set to one, the output can take on two values: 0.0 and 0.5, the latter indicating that the FIFO is at least 50% full. Given two bits of precision, the possible output values are 0.00, 0.25, 0.50 and 0.75.

106	Xilinx Development System

Image 106

Xilinx V2.1 Fifo, Block Parameters Dialog Box, Xilinx System Generator v2.1 Reference Guide, Xilinx Development System

Contents

Using the Xilinx Software Auxiliary Files Printed in U.S.AXilinx Blocks System Generator Software Features Xilinx System Generator v2.1 forXilinx System Generator v2.1 Reference Guide Manual ContentsAbout This Manual Xilinx Development SystemResource Additional ResourcesDescription/URL >> cd <your $MATLAB home directory> ConventionsTypographical Xilinx System Generator v2.1 Reference GuideIntroduction ContentsChapter Chapter 2 Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Xilinx Development SystemChapter 5 Using the Xilinx Software Chapter 4 System Generator Software FeaturesChapter 6 Auxiliary Files Xilinx System Generator v2.1 Reference Guide Chapter IntroductionIndustry and Product Overview Xilinx Development SystemIntroduction System GeneratorSystem Level Modeling with System Generator System GeneratorXilinx System Generator v2.1 Reference Guide The System Generator Design FlowXilinx Development System MATLAB Environment The System Generator Design FlowLibrary SimulinkXilinx System Generator v2.1 Reference Guide Arithmetic Data TypesXilinx Development System Hardware Handshaking Hardware HandshakingMultirate Systems IntroductionXilinx System Generator v2.1 Reference Guide Bit-Trueand Cycle-TrueModelingAutomatic Testbench Generation Xilinx Development SystemChapter Xilinx Blockset Overview What is a Xilinx Block?What is a Xilinx Block? Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide The Nature of Signals in the Xilinx BlocksetThe Block Parameters Dialog Box Xilinx Development SystemPort Data Types The Nature of Signals in the Xilinx BlocksetValid and Invalid Data Xilinx Blockset OverviewXilinx System Generator v2.1 Reference Guide Licensed CoresXilinx Development System Common Options in Block Parameters Dialog Box Common Options in Block Parameters Dialog BoxXilinx LogiCORE Versions Xilinx Blockset OverviewImplement with Xilinx Smart-IP Core if possible Use Placement Information for CoreArithmetic Type Generate CoreOverﬂow and Quantization PrecisionNumber of Bits Override with DoublesXilinx System Generator v2.1 Reference Guide Sample PeriodUse Explicit Sample Period Xilinx Development SystemSystem Generator Chapter Xilinx BlocksBasic Elements Xilinx Blocks∙Target Directory Block Parameters Dialog Box∙Xilinx Product Family ∙System Clock Period∙Generate Cores ∙Global Clock Enable and Global Clear∙Override with Doubles ∙Generate buttonXilinx System Generator v2.1 Reference Guide Addressable Shift RegisterBlock Interface Xilinx Development SystemXilinx Blocks Xilinx LogiCOREBlock Parameters Dialog Box Basic ElementsBlock Parameters Dialog Box Black BoxIncorporating mixed language black boxes Xilinx System Generator v2.1 Reference GuideFigure 3-3:Black Box block parameters dialog box Xilinx BlocksBasic Elements Block Parameters Dialog Box ConcatBlock Interface Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box ConstantConvert Xilinx BlocksXilinx System Generator v2.1 Reference Guide CounterBlock Parameters Dialog Box Figure 3-7:Convert block parameters dialog boxXilinx Blocks Basic ElementsFigure 3-8:Counter block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box DelayXilinx LogiCORE Xilinx BlocksFigure 3-11:Down sample circuit behavior Down SampleXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Get Valid BitBlock Parameters Dialog Box Basic ElementsXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-13:Mux block parameters dialog boxXilinx Blocks Parallel to SerialBlock Interface Basic ElementsXilinx System Generator v2.1 Reference Guide RegisterBlock Parameters Dialog Box Xilinx Development SystemXilinx Blocks Block InterfaceBlock Parameters Dialog Box Figure 3-16:Register block parameters dialog boxXilinx System Generator v2.1 Reference Guide ReinterpretXilinx Development System Xilinx Blocks Serial to ParallelBlock Parameters Dialog box Basic ElementsXilinx System Generator v2.1 Reference Guide Block InterfaceBlock Parameters Dialog Box Parameters speciﬁc to the block areBlock Parameters Dialog Box Set Valid BitSlice Xilinx BlocksFigure 3-21:Slice block operation Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks SyncBasic Elements Figure 3-23:Sync block use Xilinx System Generator v2.1 Reference GuideXilinx Development System Figure 3-26:Sync block parameters dialog box Block Parameters Dialog BoxXilinx Blocks Basic ElementsXilinx System Generator v2.1 Reference Guide Up SampleXilinx Development System Figure 3-29:Up Sample block parameters dialog box Block Parameters Dialog BoxXilinx Blocks Basic ElementsBlock Interface CommunicationConvolutional Encoder Xilinx System Generator v2.1 Reference GuideXilinx LogiCORE CommunicationBlock Parameters Dialog Box Xilinx BlocksFigure 3-32:Example of Depuncture block use DepunctureXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Interleaver DeinterleaverBlock Parameters Dialog Box CommunicationFigure 3-34:Forney convolutional interleaver with a constant difference between consecutive branches Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx LogiCORE Block InterfaceBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide PunctureXilinx Development System Xilinx Blocks RS DecoderBlock Parameters Dialog Box Figure 3-38:Puncture block parameters dialog boxThe port descriptions are Block InterfaceXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxCommunication Xilinx System Generator v2.1 Reference Guide g x = ∏ x –ahxGS + i i =Xilinx Development System Xilinx LogiCore RS EncoderLatency Xilinx Blocksg x = x –a0 x –a1 x –a2 . . . . x –a15 g x = x –ai x –ai + 1 . . . . x –ai + 2tc x = g x ⋅ i Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block InterfaceCommunication Parameters speciﬁc to the RS Encoder block are Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks g x = ∏ x –ahxGS + i i =Communication Xilinx LogiCore Viterbi DecoderLatency Xilinx System Generator v2.1 Reference GuideBlock Parameters Dialog Box Block InterfaceCommunication Xilinx System Generator v2.1 Reference Guide Xilinx LogiCoreXilinx Development System Xilinx Blocks Block InterfaceFigure 3-46:Pipelined decimator and interpolator Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Figure 3-47:CIC block parameters dialog boxXilinx Blocks Figure 3-49:DDS block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx LogiCORE X k = ∑ xmW N mkXilinx Blocks Block Parameters Dialog Box W N = eBlock Interface Xilinx System Generator v2.1 Reference GuideFigure 3-51 FFT Timing Diagram Block TimingXilinx Blocks Xilinx System Generator v2.1 Reference Guide Figure 3-52:FFT Timing CharacteristicsXilinx LogiCORE Xilinx Development SystemBlock Interface yn = ∑ hixn –iXilinx Blocks Figure 3-53:FIR block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemMath MathAccumulator Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Parameters speciﬁc to the block areXilinx LogiCORE AddSubBlock Parameters Dialog Box Xilinx BlocksXilinx System Generator v2.1 Reference Guide CMultBlock Parameters Dialog Box Figure 3-56:CMult block parameters dialog boxXilinx Blocks InverterXilinx LogiCORE MathXilinx LogiCORE LogicalBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Block Parameters Dialog BoxXilinx LogiCORE Figure 3-58:Logical block parameters dialog boxXilinx System Generator v2.1 Reference Guide MultBlock Parameters Dialog Box Xilinx Development SystemXilinx Blocks Xilinx LogiCOREMath Block Parameters Dialog Box NegateRelational Xilinx LogiCOREXilinx Blocks Block Parameters Dialog BoxXilinx LogiCORE MathBlock Parameters Dialog Box ScaleShift Xilinx System Generator v2.1 Reference GuideXilinx Blocks SineCosineBlock Parameters Dialog Box Figure 3-64:Shift block parameters dialog boxXilinx System Generator v2.1 Reference Guide Block Parameters Dialog BoxXilinx LogiCORE Parameters speciﬁc to the SineCosine block areXilinx Blocks ThresholdLatency Using Block Maximum CoreGateway Blocks Enabled SubsystemsMATLAB I/O Block Parameters Dialog BoxMATLAB I/O Enable AdapterGateway In Xilinx BlocksParameters speciﬁc to the Gateway In block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Gateway OutMATLAB I/O Parameters speciﬁc to the Gateway Out block are Xilinx System Generator v2.1 Reference GuideXilinx Development System Quantization Error Quantization Error BlocksClear Quantization Error DisplayBlock Interface MemoryDual Port RAM Xilinx System Generator v2.1 Reference GuideXilinx Blocks MemoryFigure 3-70:Illustration of write modes Parameters speciﬁc to the block are Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks log 2dXilinx LogiCORE DepthXilinx System Generator v2.1 Reference Guide FIFOBlock Parameters Dialog Box Figure 3-72:FIFO block parameters dialog boxXilinx Blocks Xilinx LogiCOREMemory Figure 3-73:ROM block parameters dialog box Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Xilinx LogiCORElog 2d DepthXilinx System Generator v2.1 Reference Guide Single Port RAMBlock Interface Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxMemory Figure 3-75:Illustration of write modes Xilinx System Generator v2.1 Reference GuideXilinx Development System Xilinx Blocks Xilinx LogiCORElog 2d MemoryXilinx System Generator v2.1 Reference Guide State MachineMealy State Machine Xilinx Development SystemState Machine Xilinx BlocksXilinx LogiCORE Moore State MachineBlock Parameters Dialog Box Xilinx System Generator v2.1 Reference GuideXilinx Blocks Figure 3-80:Moore State Machine block diagramState Machine Figure 3-82:Construction of Next State and Output matrices Block Parameters Dialog BoxXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Registered Mealy State MachineXilinx LogiCORE State MachineXilinx System Generator v2.1 Reference Guide Xilinx Development SystemXilinx Blocks Block Parameters Dialog BoxState Machine Xilinx LogiCORE depth = 2k 2i = 2k +width = k + o N = depth × width = k + o2k + Xilinx System Generator v2.1 Reference GuideXilinx Blocks Registered Moore State MachineState Machine Xilinx System Generator v2.1 Reference Guide Xilinx Development SystemBlock Parameters Dialog Box ds = 2k 2i = 2k +N s = ds × ws = k 2k + Xilinx Blockswhere Xilinx LogiCOREXilinx System Generator v2.1 Reference Guide Xilinx Development SystemSystem Generator Software Features Chapter System Generator Software FeaturesUsing the System Generator installer >>setupA Black Box Example Using Black BoxesInstalled System Generator directory Xilinx System Generator v2.1 Reference GuideSystem Generator Software Features Using Black BoxesBlack Box window Figure 4-1:Output of example black box functionXilinx System Generator v2.1 Reference Guide Use of mixed language projectsIncorporating mixed language black boxes Xilinx Development SystemSystem Generator Software Features Use of mixed language projectsFigure 4-2:Black Box block parameters dialog box Xilinx System Generator v2.1 Reference Guide Tips for creating a high performance designData Rate, Set ‘FAST’ Attribute Xilinx Development SystemSystem Clock Period Using the System Generator Constraints FilesUsing the System Generator Constraints Files Multicycle Path ConstraintsXilinx System Generator v2.1 Reference Guide IOB Timing and Placement ConstraintsExample for showing constraints use Figure 4-4:Example of a multirate designSystem Generator Software Features Using the System Generator Constraints FilesXilinx System Generator v2.1 Reference Guide Important IssuesConstraints Files Xilinx Development SystemFiles automatically created by System Generator Files automatically created by System GeneratorSystem Generator Software Features Xilinx System Generator v2.1 Reference Guide ∙sysgen.log - log ﬁleXilinx Development System Xilinx ISE 4.1i Project Navigator Chapter Using the Xilinx SoftwareUsing the Xilinx Software Opening a System Generator projectXilinx System Generator v2.1 Reference Guide Implementing your designXilinx Development System Using the Xilinx Software Xilinx ISE 4.1i Project NavigatorFigure 5-6:Properties of simulation process Xilinx System Generator v2.1 Reference GuideXilinx Development System Simulation Using an EDIF software ﬂowUsing an EDIF software flow Compiling your IPXilinx System Generator v2.1 Reference Guide MXE librariesXilinx Development System Xilinx software tools resources Xilinx software tools resourcesUsing the Xilinx Software Xilinx System Generator v2.1 Reference Guide Chapter Auxiliary FilesDemonstration designs Xilinx Development System>> demo Perl scriptsAuxiliary Files perl <scriptname> -hXilinx System Generator v2.1 Reference Guide Xilinx Development System