Step 5

At the [boot]: prompt, enter reboot, and press Enter. Upon reboot the managed spine will display

 

 

 

 

information similar to the following:

 

 

 

 

Unified Boot Manager For The T3 Platform.

 

 

 

 

Image Date: Jan 19 2006, 15:03:31

 

 

 

 

Checking L2 functionality...

 

 

 

 

BCM1125

 

 

 

 

L2 caches initialized and invalidated

 

 

 

 

CPU0 caches initialized

 

 

 

 

Initialized SMBUS Channels

 

 

 

 

SPD Checksum ok.

 

 

 

 

MEM_SEL = 0x00000007

 

 

 

 

CPU_REV = 0x00000001_112421FF

 

 

 

 

CPU speed = 400 MHz

 

 

 

 

IO Bridge 0,1 speed = 133, 200 MHz

 

 

 

 

Memory size = 128 MB

 

 

 

 

MC1 Configured for 128M SODIMM, CAS=2, 100 MHz

 

 

 

 

Configured Memory Size = 0x08000000

 

 

 

 

Channel Interleave Bit = 0

 

 

 

 

Number of Mem Channels = 1

 

 

 

 

Testing memory

 

 

 

 

Memory tests pass

 

 

 

 

CPU0 flushing caches

 

 

 

 

L2 flush complete

 

 

 

 

Start type = 0xBFC006A0

 

 

 

 

Jumping to romStart

 

 

 

 

Initializing HyperTransport bus

 

 

 

 

HyperTransport initialization completed

 

 

 

 

rintf MBOX connect interrupt_source=28 vector=62 status=0

 

 

 

 

Printf MBOX intEnable status=0

 

 

 

 

Found Intel Strata Flash 128 MBit (0x8918).

 

 

 

 

Mounted raw file system on device /image1. (size=6291456 bytes)

 

 

 

 

Mounted raw file system on device /image2. (size=6291456 bytes)

 

 

 

 

Mounted raw file system on device /dump0. (size=1048576 bytes)

 

 

 

 

Mounted flash file system on device /rfa1. (size=2097152 bytes)

 

 

 

 

Unified Boot Manager

 

 

 

 

[1] image1

 

 

 

 

[2] image2

 

 

 

 

CPU: Broadcom BCM1125

 

 

 

 

VxWorks Version: 5.4

 

 

 

 

[boot]:

 

 

 

 

Unified Boot Manager For The T3 Platform.

 

 

 

 

Image Date: Jan 19 2006, 15:03:31

 

 

 

 

Checking L2 functionality...

 

 

 

 

BCM1125

 

 

 

 

L2 caches initialized and invalidated

 

 

 

 

CPU0 caches initialized

 

 

 

 

Initialized SMBUS Channels

 

 

 

 

SPD Checksum ok.

 

 

 

 

MEM_SEL = 0x00000007

 

 

 

 

CPU_REV = 0x00000001_112421FF

 

 

 

 

CPU speed = 400 MHz

 

 

 

 

IO Bridge 0,1 speed = 133, 200 MHz

 

 

 

 

Memory size = 128 MB

 

 

 

 

MC1 Configured for 128M SODIMM, CAS=2, 100 MHz

 

 

 

 

Configured Memory Size = 0x08000000

 

 

 

 

Channel Interleave Bit = 0

 

 

 

 

Number of Mem Channels = 1

 

 

 

 

Testing memory

 

 

 

 

Memory tests pass

 

 

 

Cisco SFS 7012 InfiniBand Server Switch Hardware Users Guide

 

 

 

 

1-26

 

 

OL-8787-05

 

 

 

 

 

Page 36
Image 36
Cisco Systems SFS 7012 manual Information similar to the following