Bosch Appliances TTCAN user manual Ttcan =1

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

LBack	Loop Back Mode
	one	Loop Back Mode is enabled.
	zero	Loop Back Mode is disabled.
Silent	Silent Mode
	one	The module is in Silent Mode
	zero	Normal operation.
NoRAM	No Message RAM Mode
	one	IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
	zero	No Message RAM Mode disabled, normal Message RAM usage.

WdOff Disable Watchdog

one The Watchdog disabled.

zero The Watchdog is enabled, after Initialization has ﬁnished (Init = 0).

Write access to the Test Register is enabled by setting bit Test in the CAN Control Register. The different test functions may be combined, but Tx1-0≠ “00” disturbs message transfer.

2.3.4.2 Disable Watchdog Mode

The TT Application Watchdog (see chapter 3.5.6) can be disabled by programming the Test Register bit WdOff to one and the Application_Watchdog_Limit AppWdL to 0x00. When bit Test in the CAN Control Register is reset, WdOff is also reset if the TTCAN is in time triggered operating mode; if the TTCAN is in event driven CAN mode, WdOff is remains set and the TT Application Watchdog remains disabled (emulating the C_CAN function).

The TT Application Watchdog should not be disabled in a TTCAN application program.

2.3.4.3 Silent Mode

The CAN_Core can be set in Silent Mode by programming the Test Register bit Silent to one.

In Silent Mode, the TTCAN is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus and it cannot start a transmission. If the CAN_Core is required to send a dominant bit (ACK bit, overload ﬂag, active error ﬂag), the bit is rerouted internally so that the CAN_Core monitors this dominant bit, although the CAN bus may remain in recessive state. The Silent Mode can be used to analyse the trafﬁc on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). Figure 2 shows the connection of signals CAN_TX and CAN_RX to the CAN_Core in Silent Mode.

CAN_TX CAN_RX

TTCAN =1

• •

Tx Rx

CAN_Core

Figure 2: CAN_Core in Silent Mode

In ISO 11898-1, the Silent Mode is called the Bus Monitoring Mode.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Eecs RdlcTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Conﬁguration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Conﬁguration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConﬁguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF