Bosch Appliances TTCAN user manual Tmc, Det, Ecs, Sws, Wgtd

Page 38

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

TMC	Time Mark Compare
	0x0	No Time Mark interrupt is generated.
	0x1	Time Mark interrupt if (Time Mark = Cycle Time).
	0x2	Time Mark interrupt if (Time Mark = Local Time).
	0x3	Time Mark interrupt if (Time Mark = Global Time).
DET	Disable External Time Mark Port
	one	The Time Mark port is disabled.
	zero	The Time Mark port is enabled.
ECS	External Clock Synchronisation
	The External Clock Synchronisation takes effect when ‘1’ is written to ECS.
	ECS will always be read as ‘0’
SWS	Stop Watch Source (when edge is detected at the STOP_WATCH_TRIGGER pin)
	0x0	Stop Watch is disabled.
	0x1	Actual value of Cycle Time is copied to Stop_Watch.
	0x2	Actual value of Local Time is copied to Stop_Watch.
	0x3	Actual value of Global Time is copied to Stop_Watch.
WGTD	Wait for Global Time Discontinuity
	one	The node waits for the completion of a Reference Message with
		Disc_Bit = ‘1’ after SGT has been set by the CPU. GTDiff is
		locked while WGTD is set.
	zero	No Global Time Preset is pending.

SGT Set Global Time

The Global Time Preset takes effect when ‘1’ is written to SGT. SGT will always be read as ‘0’.

The Synchronisation Deviation SD is the difference between NumCfg and NumAct. When the calculated NumAct deviates by more than 2(ldSDL + 5) from NumCfg, the drift compensation is

suspended and the GTE interrupt is activated. There is no drift compensation in Level 1.

ECS schedules the updated NumCfg value for activation by the next Reference Message.

SGT schedules the GTDiff value for activation by the next Reference Message.

Setting of ECS and SGT requires EECS to be set and the node to be the actual Time Master.

3.5.21 TT Sync_Mark Register (addresses 0x69 & 0x68)

15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								Sync_Mark

					r								r
Sync_MarkSynchronisation Mark
		0x0000-0xFFFF				Cycle Time.

The TT Sync_Mark register shows the Sync_Mark captured at the Start of Frame of each message, measured in Cycle Time. The register is updated when the message becomes valid and retains its value until the next message becomes valid.

BOSCH

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11.11.02

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0TEW EecsRdlc Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TUR Numerator Conﬁguration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Conﬁguration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Conﬁguration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConﬁguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF