Bosch Appliances TTCAN user manual Cycle Time and Global Time Synchronisation

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TTCAN

User’s Manual

Revision 1.6

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(the “Micro Tick”) is incremented eight times each NTU, or, when TUR becomes <8 by drift compensation or by configuration for TTCAN Level 1, it is incremented four times each NTU.

Figure 19 describes the synchronisation of the Cycle Time and Global Time, performed in the same manner by all TTCAN nodes, including the Time Master. Any message received or transmitted invokes a capture of the Local Time taken at the message’s Frame Synchronisation Event. This Frame Synchronisation Event occurs at the Sample Point of each Start of Frame (SoF) bit and causes the Local Time to be loaded into the Sync_Mark register.

NTU

Local Time

Reference Message

Sync_Mark

 

Frame Syn-

 

Master_Ref_Mark

Ref_Mark

Sync_Mark

 

 

 

chronisation

 

 

 

 

 

 

 

Reference

Ref_Mark

 

 

 

Message Valid

 

 

 

 

 

 

 

 

 

Local Time

Local_Offset

 

Cycle Time

 

 

 

 

 

Global Time

 

Figure 19: Cycle Time and Global Time Synchronisation

 

 

Whenever a valid reference message is transmitted or received, the contents of the Sync_Mark register is loaded into the Ref_Mark register. The difference between the actual value of the Ref_Mark and the local time is the cycle time (Cycle Time= Local Time– Ref_Mark).

The Global Time exists for TTCAN Level 2 only, in Level 1 it is invalid. After Configuration, a Potential Time Master will use its own Local Time as Global Time. The time master establishes its own local time as global time by transmitting its own Ref_Marks in the Reference Message, as Master_Ref_Marks.

A node that receives a Reference Message calculates its Local_Offset to the Global Time by comparing (see figure 19) their local Ref_Mark with the received Master_Ref_Mark. The node’s view of the Global Time is Local Time + Local_Offset. In a Potential Time Master that has never received another Time Master’s Reference Message, Local_Offset will be zero. When a node becomes the current Time Master after first having received other Reference Messages, Local_Offset will be frozen at its last value. In the time receiving nodes, Local_Offset may be subject to small adjustments, due to clock drift, when another node becomes Time Master, or when there is a Global Time discontinuity, signalled by the Disc_Bit in the Reference Message. With the exception of Global Time discontinuity, the Global Time provided to the application program in the Global Time register will be smoothed by a low-pass filtering, avoiding un-reasonableness in its integer part.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0TEW EecsRdlc TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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