Bosch Appliances TTCAN Change Control, Conventions Scope References Terms and Abbreviations

Page 3

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

TTCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1. About this Document

6

1.1. Change Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.1. Current Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.2. Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2. Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3. Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.5. Terms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1. Software Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.2. CAN Message Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.3. Disabled Automatic Retransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.4. Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.4.1. Test Register (addresses 0x0B & 0x0A)

11

2.3.4.2. Disable Watchdog Mode

12

2.3.4.3. Silent Mode

12

2.3.4.4. Loop Back Mode

13

2.3.4.5. Loop Back combined with Silent Mode

13

2.3.4.6. Software control of Pin CAN_TX

14

2.3.4.7. No Message RAM Mode

14

3. Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1. Hardware Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2. CAN Protocol Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1. CAN Control Register (addresses 0x01 & 0x00) . . . . . . . . . . . . . . . . . . . . . . 17 3.2.2. Status Register (addresses 0x03 & 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2.1. Status Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3. Error Counter (addresses 0x05 & 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4. Bit Timing Register (addresses 0x07 & 0x06) . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.5. BRP Extension Register (addresses 0x0D & 0x0C) . . . . . . . . . . . . . . . . . . . 20

3.3. Message Interface Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1. IFx Command Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1.1. Direction = Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1.2. Direction = Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.2. IFx Command Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.3. IFx Message Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3.3.1. IFx Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.3.2. IFx Arbitration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.3.3. IFx Message Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.3.4. IFx Data A and Data B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.4. Message Object in the Message Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modEecs RdlcTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConfiguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF
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