Bosch Appliances TTCAN user manual Ccm, Bark, AppWdL, TT Interrupt Enable Register addresses 0x31

Page 32

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

CCM

Cycle_Count_Max (Number of last Basic Cycle in the Matrix Cycle)

 

 

 

 

 

0x00

 

1

Basic Cycle in the Matrix Cycle.

 

 

 

 

 

 

 

 

0x01

 

2

Basic Cycles in the Matrix Cycle.

 

 

 

 

 

 

 

 

0x03

 

4

Basic Cycles in the Matrix Cycle.

 

 

 

 

 

 

 

 

0x07

 

8

Basic Cycles in the Matrix Cycle.

 

 

 

 

 

 

 

 

0x0F

 

16 Basic Cycles in the Matrix Cycle.

 

 

 

 

 

 

 

 

0x1F

 

32 Basic Cycles in the Matrix Cycle.

 

 

 

 

 

 

 

 

0x3F

 

64 Basic Cycles in the Matrix Cycle.

 

 

 

 

 

 

 

 

other values

reserved.

 

 

 

 

 

 

 

 

 

 

 

3.5.6 TT Application Watchdog Limit Register (addresses 0x2F & 0x2E)

 

 

 

15

 

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bark

 

 

 

 

res

 

 

 

 

 

 

AppWdL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rw

 

 

 

r

 

 

 

 

 

 

 

rw

 

 

 

Bark

The state of the Application_Watchdog

 

 

 

 

 

 

 

 

 

 

one

 

 

The application has failed to serve the watchdog on time.

 

 

 

 

zero

 

The application did serve the watchdog on time.

 

 

 

AppWdL

Application_Watchdog_Limit

 

 

 

 

 

 

 

 

 

 

 

 

0x00-0xFF

The maximum time (unit is 256•NTU) after which the application

 

 

 

 

 

 

has to serve the watchdog again since last time it has served it.

The application watchdog is served by reading the high byte of the register. When the watchdog is not served in time, the bit Bark is set, all TTCAN communication is stopped, and the TTCAN module is set into silent mode. The TTCAN module is restarted by writing Bark to ‘0’ in configuration mode.

The application watchdog can be disabled by programming the Test Register bit WdOff to ‘1’ and AppWdL to 0x00, see chapter 2.3.4.2.

3.5.7 TT Interrupt Enable Register (addresses 0x31 & 0x30)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CfE

ApW

WTr

IWT

CEL

TxO

TxU

GTE

Dis

GTW

SWE

TMI

SoG

CSM

SSM

SBC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

There is for each bit in the TT Interrupt Vector register one corresponding enable bit in the TT Interrupt Enable register, ‘1’ meaning enabled and ‘0’ meaning disabled. The TT Interrupt Vector register bits will be updated regardless of the TT Interrupt Enable register bits, the enable bits control whether an interrupt will be generated when the matching bit in the TT Interrupt Vector register is set to ‘1’ (and when the module interrupt is enabled by IE = ‘1’ in the CAN Control register).

3.5.8 TT Interrupt Vector Register (addresses 0x33 & 0x32)

The individual TT Interrupt Vector register bits are set to ‘1’ when their specific interrupt condition is met, an interrupt will be generated as long as both an Interrupt Vector bit and the corresponding Interrupt Enable bits are set. The Interrupt Vector register bits will not be cleared automatically; with the exception of hardware reset, they can only be cleared by the CPU. The CPU cannot write the Interrupt Vector register bits to ‘1’, but it can write them to ‘0’.

BOSCH

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11.11.02

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Page 31 Page 33
Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0TEW EecsRdlc TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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