Bosch Appliances TTCAN user manual TT Cycle Count Register addresses 0x3D & 0x3C

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.5.13 TT Cycle Count Register (addresses 0x3D & 0x3C)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			reserved						res			C_Cnt5-0

			r						r				r

C_Cnt5-0Cycle_Count

0x00-0x3FThe number of the actual Basic Cycle in the System Matrix.

3.5.14 TT Error Level Register (addresses 0x3F & 0x3E)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			reserved						MSCmax			MSCmin		TTEL

			r						r			r			r

MSCmax Maximum Message Status Count

0x0-0x7The highest Message Status Count of all periodic Message Objects.

MSCmin Minimum Message Status Count

0x0-0x7The lowest Message Status Count of all periodic Message Objects.

TTEL TT Error Level

0x0 severity 0 : No Error

0x1 severity 1 : Warning

0x2 severity 2 : Error

0x3 severity 3 : Fatal Error

3.5.15 TUR Numerator Conﬁguration Low Register (addresses 0x57 & 0x56)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							NumCfgL

			rw									rw

NumCfgL TUR Numerator Conﬁguration (low part) 0x0000-0xFFFFNumCfg[15…0]

NumCfg is an 18-bit value. Its high part, NumCfg[17…16] is hard wired to 0b01. The range of NumCfg is [0x10000…0x1FFFF]. The value conﬁgured in NumCfg is the initial value for NumAct, so when the number 0xnnnn is written to NumCfg[15…0], NumAct starts with the value 0x1nnnn. NumCfgL may be written during Conﬁguration Mode or if EESC (Enable External Clock Synchronisation) is set. When a new value for NumCfgL is written after Conﬁguration Mode, the new value takes effect when the ECS bit of the TT Clock Control register is written to ‘1’.

Note : The actual value of TUR may be changed by the clock drift compensation function of TTCAN Level 2 in order to adjust the node’s local view of the NTU to the time master view of the NTU. DenomCfg will not be changed by the automatic drift compensation, NumAct may be adjusted in the range of the Synchronisation Deviation Limit around NumCfg. NumCfg and DenomCfg should be programmed to the largest suitable values in order to allow the best computational accuracy for the drift compensation process.

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modTEW EecsRdlc AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TUR Numerator Conﬁguration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Conﬁguration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConﬁguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConﬁgurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF