Bosch Appliances TTCAN user manual Propagation Time Segment, Brp

Page 46

TTCAN

User’s Manual

Revision 1.6

A given bit rate may be met by different bit time configurations, but for the proper function of the CAN network the physical delay times and the oscillator’s tolerance range have to be considered.

Parameter

Range

Remark

 

 

 

BRP

[1 … 32]

defines the length of the time quantum tq

Sync_Seg

1 tq

fixed length, synchronisation of bus input to system clock

Prop_Seg

[1 … 8] tq

compensates for the physical delay times

Phase_Seg1

[1 … 8] tq

may be lengthened temporarily by synchronisation

Phase_Seg2

[1 … 8] tq

may be shortened temporarily by synchronisation

SJW

[1 … 4] tq

may not be longer than either Phase Buffer Segment

This table describes the minimum programmable ranges required by the CAN protocol

Table 1 : Parameters of the CAN Bit Time

4.2.1.2 Propagation Time Segment

This part of the bit time is used to compensate physical delay times within the network. These delay times consist of the signal propagation time on the bus and the internal delay time of the CAN nodes.

Any CAN node synchronised to the bit stream on the CAN bus will be out of phase with the transmitter of that bit stream, caused by the signal propagation time between the two nodes. The CAN protocol’s non-destructive bitwise arbitration and the dominant acknowledge bit provided by receivers of CAN messages require that a CAN node transmitting a bit stream must also be able to receive dominant bits transmitted by other CAN nodes that are synchronised to that bit stream. The example in figure 10 shows the phase shift and propagation times between two CAN nodes.

manual_about.fm

Sync_Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

Node B

 

 

 

 

 

Delay A_to_B

Delay B_to_A

Node A

 

 

 

 

Delay A_to_B >= node output delay(A) + bus line delay(A→B) + node input delay(B)

Prop_Seg

>= Delay A_to_B + Delay B_to_A

 

Prop_Seg

>= 2 • [max(node output delay+ bus line delay + node input delay)]

Figure 10: The Propagation Time Segment

In this example, both nodes A and B are transmitters performing an arbitration for the CAN bus. The node A has sent its Start of Frame bit less than one bit time earlier than node B, therefore node B has synchronised itself to the received edge from recessive to dominant. Since node B has received this edge delay(A_to_B) after it has been transmitted, B’s bit timing segments are shifted with regard to A. Node B sends an identifier with higher priority and so it will win the arbitration at a specific identifier bit when it transmits a dominant bit while node A

BOSCH

- 46/77 -

11.11.02

Page 45 Page 47
Image 46
Page 45 Page 47
Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0Rdlc EecsTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan Timing510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
Top Page Image Contents